Abstract: Aspects of the present disclosure include methods, apparatuses, and computer readable media for determining a connected mode discontinuous reception (C-DRX) short cycle value, transmitting a C-DRX short cycle request to a base station, the C-DRX short cycle request including the C-DRX short cycle value, receiving a first confirmation indicating the base station accepting the C-DRX short cycle value associated with the C-DRX short cycle request, determining an averaging window value based on the C-DRX short cycle value, transmitting an averaging window request to the base station, the averaging window request including the averaging window value, receiving a second confirmation indicating the base station accepting the averaging window value associated with the averaging window request, and communicating with the base station based on the C-DRX short cycle value and the averaging window value.

Abstract: Disclosed are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel drive circuit and a light emitting device connected to the pixel drive circuit, the pixel drive circuit includes a plurality of transistors, wherein at least one transistor includes an active layer and two gate electrodes. The substrate is provided with a semiconductor layer and a plurality of conductive layers disposed on one side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and there is an overlapping region between an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer between the two gate electrodes on the substrate.

Abstract: A display substrate includes a base substrate, including a display region; multiple sub-pixels including first sub-pixels and second sub-pixels adjacent along a first direction, located in the display region, each including a pixel circuit structure; a light-shielding layer, located between the pixel circuit structure and the base substrate, provided with a light transmission hole; a first initialization signal line and a light emitting control signal line extending along the first direction; a first power supply line, extending along a second direction; a first data line, extending along the second direction, connected with the pixel circuit structure of the first sub-pixel; and a second data line, extending along the second direction, connected with the pixel circuit structure of the second sub-pixel; the hole is located within a region enclosed by the first power supply line, the second data line, the light emitting control signal line, and the first initialization signal line.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of initialization signal lines and a plurality of connection lines. The initialization signal lines are arranged in a first conductive layer, extend along a first direction and are arranged at intervals along a second direction; the connection lines are arranged in a second conductive layer, extend along the second direction and are arranged at intervals along the first direction; the first conductive layer and the second conductive layer are an identical layer or different layers; projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate are intersected and electrically connected, such that the projections of the initialization signal lines and the connection lines on the base substrate form a grid structure.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a pixel unit, including a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor and a threshold compensation transistor; a first power line configured to supply a first power supply voltage to the pixel circuit; a blocker, electrically connected with the first power line; and a first conductive structure, connected with the gate electrode of the driving transistor, the first channel and the second channel of the threshold compensation transistor are connected by a conductive connection portion; an area of an orthographic projection of a portion of the blocker overlapping with the first conductive structure on the base substrate is larger than an area of an orthographic projection of a portion of the blocker overlapping with the conductive connection portion on the base substrate.

Abstract: A display panel includes: a substrate; at least one first signal line disposed on the substrate and located in a peripheral region; at least one second signal line disposed on the substrate and located in the peripheral region; an insulating layer covering the at least one first signal line and the at least one second signal line; and a shielding signal line covering the at least one groove. The at least one second signal line and the at least one first signal line are arranged in a same layer. A surface of the insulating layer away from the substrate has at least one groove. An orthogonal projection, on the substrate, of a bottom surface of a groove is located between orthogonal projections, on the substrate, of a first signal line and a second signal line.

Abstract: A display substrate and a display device are disclosed. The display substrate includes: a a transition region, located between a first display region and a second display region, the first display region, the second display region and the transition region are provided with a plurality of pixels, the plurality of pixels are arranged in an array in the first direction and a second direction intersecting with the first direction, a pixel per inch (PPI) of the first display region is greater than a PPI of the second display region and a PPI of the transition region, the transition region is further provided with a row driving circuit, the row driving circuit is configured to drive the plurality of pixels in the first display region, the second display region and the transition region by rows.

Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate; a pixel unit on the base substrate and including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit being closer to the base substrate than the light-emitting element and including a driving transistor; a data line configured to provide data signal to the pixel circuit; a connection element through which the light-emitting element is connected with the pixel circuit, the connection element including a shielding portion; and a connection line connected with a gate electrode of the driving transistor. The data line includes two adjacent data lines with the shielding portion located therebetween, and an orthographic projection of the connection line on the base substrate at least partially overlaps with an orthographic projection of the shielding portion on the base substrate.

Abstract: The present disclosure relates to a display panel and a curved display device. The display panel includes a flexible substrate (100), including a first region (BB) and a second region (AA). The first region (BB) includes: a plurality of light emitting structures (110) with a first opening gap (200) formed between two adjacent light omitting structures (110); and a plurality of flexible bridging parts (120), with at least one flexible bridging part (120) connecting two adjacent light emitting structures (110).

Abstract: A display substrate and a display device. The display substrate includes: a plurality of pixel islands, a first opening, a second opening and a first passage region. Each pixel island includes at least one pixel, each pixel includes a plurality of first driving lines, the first passage region is provided with a plurality of first connection lines, each of the plurality of pixel islands further includes a plurality of transfer lines, and the plurality of transfer lines are arranged in different layers from the plurality of first driving lines and cross each other to form a plurality of overlapping regions; the plurality of transfer lines are electrically connected with the plurality of first driving lines through via holes located in part of the overlapping regions, and the transfer lines in two adjacent pixel islands are respectively connected with the plurality of first connection lines in the first passage region.

Abstract: This disclosure relates to a virtual object control method. The method includes: displaying, by an electronic device, a first live streaming resource, the first live streaming resource including at least one selectable virtual object and at least one virtual object controlled by an anchor user; transmitting a control request when receiving a selection instruction for a target virtual object in the at least one selectable virtual object, the control request being for requesting to control the target virtual object; and controlling, in response to a control instruction for the target virtual object, the target virtual object to perform a target operation. With the foregoing method, viewer users can participate in live streaming when watching the live streaming, thereby improving the level of participation of the viewer users, and increasing interaction between the viewer users and the anchor user.

Abstract: A display panel includes an array substrate and an encapsulation layer encapsulated on a surface of the array substrate. The display panel further includes a stretching area located in a corner area of the display panel and at least partially located in a display area of the display panel, and the stretching area is provided with a hollow opening penetrating through the array substrate and the encapsulation layer.

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.

Abstract: Aspects of the present disclosure can receive a hardware Vsync signal from a display, generate a hardware timestamp signal based on the hardware Vsync signal, determine an error for a pulse in the hardware timestamp signal, determine whether the error for the pulse is over a threshold, synchronize a software Vsync signal based on the hardware timestamp signal, wherein the pulse of the hardware timestamp signal is ignored in synchronization based on whether the error is above the threshold, and control rendering and transmission of a frame to the display based on the synchronized software Vsync signal.

Abstract: A flexible array substrate includes at least one stretchable region; wherein the flexible array substrate is provided with a plurality of through holes within the stretchable region, and the plurality of through holes divide the stretchable region into a pixel island area for displaying and a bridging area for signal transmission; the bridging area includes a source-drain bridging area. The flexible array substrate, in the source-drain bridging area, includes: a base substrate, a first source-drain metal layer, a first insulating material layer, a second source-drain metal layer, a second insulating material layer, and an encapsulation layer that are sequentially stacked.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a non-stretchable display region and a stretchable display region. The stretchable display region includes multiple island regions in an array and separated from each other, and multiple bridge regions connecting adjacent island regions, a pixel unit is arranged on each of the island regions, the pixel unit includes at least one pixel, and a signal wire electrically connecting the pixels is arranged on each bridge region. A pixel pitch between the pixels in the pixel unit in a stretching direction is a reference pitch P0, a pitch between two adjacent pixel units in the stretching direction is a first pitch P1, and the first pitch P1 is less than the reference pitch P0.

Abstract: A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.

Abstract: A display panel and a display device. The display panel comprises a transition region, and further comprises: a base substrate; multiple pixel units located on the side of the base substrate and integrated in the transition region; and a first gate drive circuit located on the side of the base substrate facing the pixel units, integrated in the transition region, and comprising a first shift register unit and a first signal line group. The first signal line group comprises a first signal line segment group used for providing a drive signal for the first shift register unit. The base substrate comprises multiple integration portions which are located between orthographic projections of two adjacent pixel units in the same row on the base substrate.

Abstract: The display panel includes a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, a same row of pixel circuits corresponds to two rows of gate lines, and one/the other row of gate line is electrically connected to odd/even-numbered columns of pixel circuits in the row of pixel circuits, and provides a corresponding gate driving signal for the odd/even-numbered columns of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one/the other column of data line of the two columns of data lines is electrically connected to odd/even-numbered rows of pixel circuits, and provides a corresponding data voltage for the odd/even-numbered rows of pixel circuits.

Abstract: The present application discloses a display panel and a display device. The display panel includes: a base substrate; a reference power line, arranged in a non-display area and including a first electrode metal layer and a second electrode metal layer which are arranged on the base substrate in sequence in a stacked manner; and an encapsulating structure, arranged on a side, deviating from the base substrate, of the reference power line; where in the reference power line, a projection of the second electrode metal layer on the base substrate is arranged within a projection of the encapsulating structure on the base substrate, and a projection of the first electrode metal layer on the base substrate goes beyond an edge of the projection of the encapsulating structure on the base substrate.