Abstract: Methods and apparatuses are provided for alignment of hardware and software Vsync signals through filtering out delayed timestamp signals in a hardware timestamp signal used to generate the software Vsync. The alignment may occur when a display client is operating in a video mode but not a command mode. A compositor or processing unit may receive a hardware Vsync signal from a display using a video mode, generate a hardware timestamp signal based on the hardware Vsync signal, determine a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames, determine whether the delay for the pulse is over a threshold, and control rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold. Thus, accurate Vsync signal synchronization may occur.

Abstract: The display panel includes a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, a same row of pixel circuits corresponds to two rows of gate lines, and one/the other row of gate line is electrically connected to odd/even-numbered columns of pixel circuits in the row of pixel circuits, and provides a corresponding gate driving signal for the odd/even-numbered columns of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one/the other column of data line of the two columns of data lines is electrically connected to odd/even-numbered rows of pixel circuits, and provides a corresponding data voltage for the odd/even-numbered rows of pixel circuits.

Abstract: Disclosed are a display panel and a display device. The display panel includes: a pixel unit, including a pixel circuit and a light-emitting element, the pixel circuit includes a driving transistor and a threshold compensation transistor; a first power line configured to supply a first power supply voltage to the pixel circuit; a blocker, electrically connected with the first power line; and a first conductive structure, connected with the gate electrode of the driving transistor, the first channel and the second channel of the threshold compensation transistor are connected by a conductive connection portion; an area of an orthographic projection of a portion of the blocker overlapping with the first conductive structure on the base substrate is larger than an area of an orthographic projection of a portion of the blocker overlapping with the conductive connection portion on the base substrate.

Abstract: The embodiments of the present disclosure provides a display substrate, including: an active region and a peripheral region, the active region is provided therein with a plurality of pixel units arranged in an array, all the pixel units are divided into n pixel unit groups, the peripheral region is provided therein with a driver block including a first gate drive circuit having n+x first signal output terminals configured to sequentially output first gate drive signals in an active level and the first gate line provided for an ith pixel unit group is electrically connected to a (i+x)th first signal output terminal, and the reset signal line provided for the ith pixel unit group is electrically connected to an ith first signal output terminal, with i being a positive integer and i?n.

Abstract: A display substrate and a display device are provided. The display substrate includes a shift register unit, a first clock signal line and a first power line, the shift register unit includes a charge pump circuit, and the charge pump circuit includes a first capacitor, a first transistor and a second capacitor. The charge pump circuit is electrically connected with a first input node and a first node, respectively. A first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a first electrode plate of the second capacitor is connected with the first power line, a second electrode plate of the second capacitor is connected with the first node, a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor.

Abstract: Disclosed is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, the gate drive circuit includes a plurality of cascaded shift register units, and a shift register unit is connected with at least one power supply line. The shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected with a first group of clock signal lines, and the second output circuit is connected with the first group of clock signal lines and a second group of clock signal lines. In a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit.

Abstract: The present disclosure relates to a display panel and a curved display device. The display panel includes a flexible substrate (100), including a first region (BB) and a second region (AA). The first region (BB) includes: a plurality of light emitting structures (110) with a first opening gap (200) formed between two adjacent light omitting structures (110); and a plurality of flexible bridging parts (120), with at least one flexible bridging part (120) connecting two adjacent light emitting structures (110).

Abstract: A pixel circuit, a driving method therefor and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a write sub-circuit, a compensation sub-circuit, a reset sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a leak-proof sub-circuit, a storage sub-circuit and a light-emitting element. The reset sub-circuit is configured to reset a fourth node under control of a signal of a light-emitting control signal terminal and reset a fifth node under control of a signal of a reset control signal terminal. The compensation sub-circuit is configured to compensate a threshold voltage of the driving sub-circuit to the fifth node under the control of a signal of a first scanning signal terminal. The leak-proof sub-circuit is configured to write a signal of the fifth node into a first node under control of a signal of a second scanning signal terminal.

Abstract: Aspects of the present disclosure can receive a hardware Vsync signal from a display, generate a hardware timestamp signal based on the hardware Vsync signal, determine an error for a pulse in the hardware timestamp signal, determine whether the error for the pulse is over a threshold, synchronize a software Vsync signal based on the hardware timestamp signal, wherein the pulse of the hardware timestamp signal is ignored in synchronization based on whether the error is above the threshold, and control rendering and transmission of a frame to the display based on the synchronized software Vsync signal.

Abstract: The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units including a plurality of sub-pixels. The array substrate includes: a plurality of power lines which are arranged in a conductive layer on a base substrate, are arranged at intervals along a first direction and extend along a second direction, and are used for providing power signals to the sub-pixels; and a plurality of power leads which are arranged in another conductive layer, are arranged at intervals along the second direction and extend along the first direction. Projections of at least one of the power lines and at least one of the power leads on the base substrate intersect, and the projections of the power lines and the power leads on the base substrate form a grid-like structure.

Abstract: Please replace the abstract originally filed with the following: A display panel and a display device. Because the pixel distribution density in a second display subarea (A12) is lower than that in a first display subarea (A11), the quantities of sub-pixels (pix) connected to scanning lines are not completely the same; a sub-pixel row having the greatest quantity of sub-pixels (pix) in the display panel is taken as a reference sub-pixel row, the quantity of the sub-pixels (pix) of the reference sub-pixel row is taken as a reference value, a sub-pixel row having the quantity of sub-pixels (pix) smaller than the reference value is taken as a compensation sub-pixel row, and a scanning line connected to the compensation sub-pixel row is taken as a first scanning line; the display panel is provided with load compensation units corresponding to at least part of the first scanning lines, and the load compensation units are located in the second display subarea.

Abstract: A shift register circuit includes a first control sub-circuit and a first output sub-circuit. The first control sub-circuit is configured to: adjust a voltage of a first node to a turn-on voltage due to an influence of a first direct current voltage signal from a first clock signal terminal, an initial voltage signal from an initial signal terminal and a second direct current voltage signal from a second clock signal terminal; and maintain the voltage of the first node at the turn-on voltage due to an influence of a first clock signal from the first clock signal terminal and a second clock signal from the second clock signal terminal. The first output sub-circuit is configured to be turned on under a control of the turn-on voltage of the first node to transmit a first voltage signal from a first voltage terminal to a signal output terminal.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for composition strategy searching based on dynamic priority and runtime statistics. A CPU may determine, based on a plurality of frames, a usage frequency of each of one or more composition groups. The one or more composition groups may be used for composing the plurality of frames. The CPU may subsequently assign/update a priority for each of the one or more composition groups based on the usage frequency, such that the CPU may analyze, as part of a frame composition procedure, at least one of the one or more composition groups in an order that is based on the priority of the one or more composition groups.

Abstract: A display substrate includes a base, and first data lines, second data lines, a plurality of sub-pixels and voltage signal lines disposed on the base. The first data lines and the second data lines are alternately arranged in a first direction. Each column of sub-pixels includes first sub-pixels and second sub-pixels that are alternately arranged in a second direction. In the column of sub-pixels, the first sub-pixels are electrically connected to a first data line located on a side of the column of sub-pixels and adjacent thereto, and the second sub-pixels are electrically connected to a second data line located on another side of the column of sub-pixels and adjacent thereto. An orthogonal projection of each voltage signal line on the base is located between orthogonal projections of a first data line and a second data line between two adjacent columns of sub-pixels on the base.

Abstract: The present disclosure relates to a pixel drive circuit, a driving method thereof, and a display panel, which relates to the field of display technology. The source, drain and gate of the drive transistor of the pixel drive circuit are respectively connected to the first node, the second node and the third node. The storage capacitor is connected to the third node. The first control unit is used for enabling a path between the second node and the fourth node in response to the first control signal. The second control unit is used for outputting the first power supply voltage to the first node in response to the light-emitting signal. The threshold compensation transistor is used for enabling a path between the second node and the third node in response to the second control signal. The material of the active region is a metal oxide semiconductor.

Abstract: A display panel and a display device. The display panel comprises a transition region, and further comprises: a base substrate; multiple pixel units located on the side of the base substrate and integrated in the transition region; and a first gate drive circuit located on the side of the base substrate facing the pixel units, integrated in the transition region, and comprising a first shift register unit and a first signal line group. The first signal line group comprises a first signal line segment group used for providing a drive signal for the first shift register unit. The base substrate comprises multiple integration portions which are located between orthographic projections of two adjacent pixel units in the same row on the base substrate.

Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate; a pixel unit on the base substrate and including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit being closer to the base substrate than the light-emitting element and including a driving transistor; a data line configured to provide data signal to the pixel circuit; a connection element through which the light-emitting element is connected with the pixel circuit, the connection element including a shielding portion; and a connection line connected with a gate electrode of the driving transistor. The data line includes two adjacent data lines with the shielding portion located therebetween, and an orthographic projection of the connection line on the base substrate at least partially overlaps with an orthographic projection of the shielding portion on the base substrate.

Abstract: The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of initialization signal lines and a plurality of connection lines. The initialization signal lines are arranged in a conductive layer, extend along a first direction and are arranged at intervals along a second direction, and are used to provide initialization signals to the sub-pixels. The connection lines are arranged in another conductive layer, extend along the second direction and are arranged at intervals along the first direction. Projections of at least one initialization signal line and at least one connection line on the base substrate intersect, and the at least one initialization signal line and the at least one connection line are connected through a via hole, so that the projections of the initialization signal lines and the connection lines on the substrate form a grid-like structure.

Abstract: A display panel and a display apparatus are provided. The display panel includes an active area and a non-active area located at least on one side of the active area, wherein the non-active area includes a first fanout area; a plurality of sub-pixels located in the active area; a plurality of data lines located in the active area and extending from the active area to the first fanout area, the plurality of data lines electrically connected to the plurality of sub-pixels and configured to provide data signals for the plurality of sub-pixels; the first fanout area includes at least two data line fanout sub-areas, and the plurality of data lines are respectively located in the at least two data line fanout sub-areas.

Abstract: A display panel and a display device are provided. The display panel has a display area. The display panel includes: a base substrate; a driving circuit and at least one signal line on the base substrate; and at least one insulating layer between the driving circuit and the at least one signal line. The driving circuit is disposed in a periphery of the display area; and an orthogonal projection of at least one of the signal lines on the base substrate has an overlapping area with an orthogonal projection of the driving circuit on the base substrate.