Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

Abstract: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

Abstract: Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: A protection device for protecting an electrical installation, which protection device is designed to be connected in parallel with the electrical installation and includes at least two electrically conductive contact members (3, 4) that are suitable for going from a closed position to an open position when a current (I) of magnitude greater than a predetermined threshold value passes through the protection device (1), said protection device being characterized in that, in the closed position, the contact members are separated from each other by a potentially insulating piece (15), thereby forming a spark gap (E) for protecting from voltage surges between the contact members (3, 4). The invention also relates to apparatus for protecting electrical installations.

Abstract: A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

Abstract: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

Abstract: Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in current that occur during logical built-in self testing (LBIST) operations in integrated circuits. The method includes executing a first logical built-in self test sequence for a first logic region within an integrated circuit, subsequently executing a second logical built-in self test sequence for a second logic region within the integrated circuit, wherein the second test sequence is offset from the first test sequence by one or more clock cycles.

Abstract: A method implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

Abstract: A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Abstract: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

Abstract: A snack dough that can be sheeted, shaped, and fried to produce a snack product having an expanded texture, decreased external foaminess, and a lighter eating quality. In one embodiment, the dough comprises: (a) from about 0.1% to about 4% added potato fiber; (b) from about 35% to about 85% starch-based material; and (c) from about 10% to about 50% added water. In another embodiment, the dough comprises: (a) from about 0.1% to about 30% added potato fiber, wherein said added potato fiber comprises from about 30% to about 80% starch; (b) from about 35% to about 85% starch-based material; and (c) from about 10% to about 50% added water. The dough can be formed into snack pieces and cooked to form a snack product, preferably fabricated chips. Preferably, the added potato fiber comprises from about 2% to about 13% protein. The preferred starch-based material comprises from about 25% to about 100% potato flakes. Preferably, the fabricated chip is cooked by frying in oil.

Abstract: A device and method for securing terminal equipment connected to a communications line is disclosed. The device, when inserted into the communications line between the caller and terminal equipment, places an air gap in the communications line physically preventing unauthorized callers from accessing the equipment. The device employs an authentication line separate from the communications path that is used to authenticate the caller wishing to use the terminal equipment. The caller must first call the authentication line where the information regarding the source of the caller is retrieved and stored. Once the caller's source is identified, the device answers the line and requires that the caller enter an authentication code. If a proper authentication code is entered, the device disconnects the authentication line and waits a predetermined amount of time for a call on the communications line.

Abstract: A clamp comprising first and second pivotally connected jaws, each having an inner surface facing the other. According to the invention, in the closed position of the tool, the inner surfaces of the jaws, define between them, a crimping profile in the shape of an elongate "V"-shaped gap.

Abstract: The invention relates to a device for increasing the stability, especially the lateral stability, of a helicopter placed on board (1) having a tricycle landing gear (2, 6), when it is set down on a moving platform.The device comprises two lateral stabilizers (13), each equipped with a wheel (16) for support on the platform and connected to the structure of the helicopter by an essentially rigid support, comprising a leg (17), about the axis of which the wheel (16) can turn, the leg (17) itself being connected to the structure by a rigid and transverse component which may be a pivot axle if the leg can be raised, or a slidingly fitted arm if the stabilizer (13) is additional. The stabilizers may also be integrated into a towing trolley.Application to the equipment of helicopters placed on board, having a tricycle landing gear.

Abstract: A device for maneuvering a machine supported by a principal landing gear and at least one swingable wheel, such as a helicopter, between two given zones on a platform such as an alighting area and a parking area on the deck of a ship. The device includes at least one guide rail (5, 6), a hauling mechanism (12, 13, 14, 19, 20) intended to pull the machine (H), and a bar (19) for orienting the path of the machine (H). One end of the bar slides along the guide rail (5). The device also has at least one holding trolley (28) associated with means of connection (30, 31, 32, 33, 34, 35, 38, 39) to the machine (H). These means of connection make it possible to center and align the machine (H) on the guide rail (5, 6) as it is being hauled.