Patents by Inventor Louis C. Parrillo

Louis C. Parrillo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200258940
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Application
    Filed: January 6, 2020
    Publication date: August 13, 2020
    Inventors: Lidia Vereen, Bruce Lynn Bateman, David Alan Eggleston, Louis C. Parrillo
  • Patent number: 10529778
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 7, 2020
    Assignee: Unity Semiconductor Corporation
    Inventors: Lidia Vereen, Bruce L. Bateman, David A. Eggleston, Louis C. Parrillo
  • Patent number: 10448763
    Abstract: Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: October 22, 2019
    Inventor: Louis C. Parrillo
  • Publication number: 20190051701
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Application
    Filed: July 23, 2018
    Publication date: February 14, 2019
    Inventors: Lidia Vereen, Bruce L. Bateman, David A. Eggleston, Louis C. Parrillo
  • Patent number: 10050086
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 14, 2018
    Assignee: Unity Semiconductor Corporation
    Inventors: Lidia Vereen, Bruce L. Bateman, David A. Eggleston, Louis C. Parrillo
  • Publication number: 20170095094
    Abstract: Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.
    Type: Application
    Filed: December 13, 2016
    Publication date: April 6, 2017
    Inventor: LOUIS C. PARRILLO
  • Publication number: 20170033158
    Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 2, 2017
    Inventors: Lidia Vereen, Bruce L. Bateman, David A. Eggleston, Louis C. Parrillo
  • Patent number: 9549624
    Abstract: Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: January 24, 2017
    Inventor: Louis C. Parrillo
  • Publication number: 20160081496
    Abstract: Embodiments disclosed herein describe systems and methods for a hanging device including slides configured to align the hanging device at desired positions with the frame and on a wall. Embodiments may be configured to be aligned with a frame in both horizontal and vertical directions.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 24, 2016
    Inventor: LOUIS C. PARRILLO
  • Patent number: 5527739
    Abstract: A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: June 18, 1996
    Assignee: Motorola, Inc.
    Inventors: Louis C. Parrillo, Jeffrey L. Klein
  • Patent number: 5442553
    Abstract: A transceiver and additional memory are connected to the microprocessor in a vehicle so that all, or selected portions, of operating data is stored in the memory and periodically transmitted to a remote station. The data is diagnosed at the remote station and, for minor repairs, a fix is transmitted back to the vehicle. The information for a large population of vehicles is used by the manufacturer to determine if a problem is generic to a specific model and to generate repairs and/or model changes.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: August 15, 1995
    Assignee: Motorola
    Inventor: Louis C. Parrillo
  • Patent number: 5442235
    Abstract: A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: August 15, 1995
    Assignee: Motorola Inc.
    Inventors: Louis C. Parrillo, Jeffrey L. Klein
  • Patent number: 5208168
    Abstract: Adjacent buried contacts (11, 12, 13) formed at the principal surface of a well or substrate region (14) of a semiconductor device, each having a doped contact region (29, 30 31) of one conductivity type and a punch-through prevention region (36, 37, 38) of the opposite conductivity type surrounding the lower portion of the doped contact region are provided. The punch-through prevention region may advantageously be of the same conductivity type as the substrate. By performing an extra implant or other impurity introduction step while the mask to etch the contacts through the dielectric layer remains in place, the procedure to provide punch-through protected buried contacts may be easily integrated into current processes without the need for an extra mask. Such a structure and procedure enables buried contacts to be spaced closely together without over-doping the well region (14) in which source-drain regions (40, 42, 44, 46) are also formed thus avoiding a degradation in device performance.
    Type: Grant
    Filed: November 26, 1990
    Date of Patent: May 4, 1993
    Assignee: Motorola, Inc.
    Inventors: Louis C. Parrillo, Neil B. Henis, Richard W. Mauntel
  • Patent number: 4951100
    Abstract: A lightly-doped drain (LDD) structure has conductive shield overlying the lightly-doped drain and source portions to collect and/or remove hot carriers which can otherwise cause instabilities such as gain degradation and threshold voltage shifts in short-channel MOS devices. The hot carriers eventually deteriorate the performance of the transistor to the point where the transistor provides insufficient performance. Thus, the lifetime of a transistor is affected by the degradation caused by the formation of hot carriers. The lifetime is increased by collecting the hot carriers in the conductive material over the lightly-doped source and drain.
    Type: Grant
    Filed: July 3, 1989
    Date of Patent: August 21, 1990
    Assignee: Motorola, Inc.
    Inventor: Louis C. Parrillo
  • Patent number: 4929565
    Abstract: A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.
    Type: Grant
    Filed: October 30, 1989
    Date of Patent: May 29, 1990
    Assignee: Motorola, Inc.
    Inventor: Louis C. Parrillo
  • Patent number: 4889825
    Abstract: A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level.
    Type: Grant
    Filed: January 25, 1988
    Date of Patent: December 26, 1989
    Assignee: Motorola, Inc.
    Inventor: Louis C. Parrillo
  • Patent number: 4812418
    Abstract: An electronic process is provided for creating a small dimensioned pattern in a semiconductor device. In one embodiment, the pattern functions to electrically separate two areas of the substrate by less than a micron. A lithographic mask which does not have to utilize dimensions as small as those being formed on the semiconductor device is used to form a predetermined pattern with at least one separation region by irradiating and developing a photoresist material. A layer of buffer material below the photoresist material reacts with a reactive ion etch to form a separation area with sloping sides comprised of polymer filaments produced from the reaction. The sloped sides of the separation region provide a separation dimension in the substrate of the semiconductor structure which is significantly smaller than a corresponding dimension required to be implemented on the lithographic mask.
    Type: Grant
    Filed: November 27, 1987
    Date of Patent: March 14, 1989
    Assignee: Motorola, Inc.
    Inventors: James R. Pfiester, Louis C. Parrillo, J. William Dockrey
  • Patent number: 4808555
    Abstract: A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process versatility in incorporating implantation steps and patterning steps between formation of the thin layers of conductive material. Direct transfer from dielectric layer formation to conductive material layer formation steps, and performing the intermediate process steps in the same piece of equipment as the thin conductive layer formation assists in adhesion of the thin layers to each other to form the total conductive material layer. The use of in situ doped semiconductor material, such as in situ doped polycrystalline silicon and in situ doped amorphous silicon reduces the exposure of other dopants that may be present to thermal cycles of high temperature, greater than 900.degree. C., that causes these dopants to migrate undesirably.
    Type: Grant
    Filed: July 10, 1986
    Date of Patent: February 28, 1989
    Assignee: Motorola, Inc.
    Inventors: Richard W. Mauntel, Stephen J. Cosentino, Louis C. Parrillo, Patrick J. Holly
  • Patent number: 4808543
    Abstract: A bulge well structure for trench devices in wells of a conductivity type opposite to that of the substrate where the bottom of the trench has localized, extra doping. The additional doping into the bottom of the trench prior to device formation may be implanted while the photoresist mask for the trench formation is still in place. In one embodiment of the method, the trenches and the bulge or well extension formations at their bottoms are created before isolation regions are formed. The structure and method permit increased doping only where needed and are compatible with thin epitaxial layers and sharp transition interfaces of epitaxy with substrate for optimum latchup protection. No extra masks are required and the tight packing allowed by trench technology is not altered. Protection against soft errors and junction leakage by forming DRAM trench capacitors in a well of opposite conductivity type from the substrate may be provided.
    Type: Grant
    Filed: May 7, 1986
    Date of Patent: February 28, 1989
    Assignee: Motorola, Inc.
    Inventors: Louis C. Parrillo, Richard W. Mauntel, John M. Barden
  • Patent number: 4801555
    Abstract: A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.
    Type: Grant
    Filed: January 14, 1987
    Date of Patent: January 31, 1989
    Assignee: Motorola, Inc.
    Inventors: Patrick J. Holly, Louis C. Parrillo, Frank K. Baker