Abstract: An illuminated paper cutter comprising an opaque cutting board having a cutting edge at one side, a cutting blade pivotally attached to the cutting board to coact with the cutting edge to cut material placed between the cutting blade and the cutting edge, and an illuminator attached to the cutting board to illuminate the cutting edge from below, the illuminator being located so as to not extend beyond the outside edge of the cutting edge.

Abstract: A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed.The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

Abstract: The present invention relates to a CMOS structure, and method for forming the same, which prevents latchup in MOS devices. The method is directed to the CMOS structure and functions to reduce the lateral resistance of the n-tub, where the presence of a large lateral resistance in the n-tubs of prior art arrangements, has been found to cause latchup. A retrograde n.sup.+ region is formed at a predetermined location in the n-tub using proton bombardment to increase the n-type donor concentration at this predetermined location in the n-tub and thus significantly reduce the lateral resistance associated with the n-tub. By reducing this resistance, the parasistic SCR action between the two types of bipolar devices will be lessened, since the lower resistance of the n-tub reduces the IR drop associated with the parasitic device located in the n-tub. A beam of hydrogen ions, or doubly ionized helium, is used as the proton source. The n.sup.

Abstract: A process is disclosed for fabricating LDD CMOS structures having a reduced mask count and improved manufacturability. In one embodiment of the invention a CMOS structure is formed having gate insulators overlying N and P type surface regions. Gate electrodes are formed on each of the surface regions and a spacer forming material is deposited over the electrodes and the surface regions. The spacer material is anisotropically etched from one of the surface regions to form spacers at the edge of the first gate electrode while retaining the spacer forming material over the second surface region. Source and drain regions of the first MOS transistor are implanted using the spacers as an implantation mask. The spacers are removed and a lightly doped source and drain is implanted using the gate electrode as a mask. The implanted source and drain regions are oxidized using the remaining spacer forming material as an oxidation mask to prevent oxidation of the second surface region.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDS) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Conformal materials such as CVD polysilicon may also be employed for this purpose. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implantation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation.

Abstract: A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask.

Abstract: A two-device trench cell having a transistor surrounded by a capacitor. This combined capacitor and transistor cell can be used as a memory cell. The capacitor is first fabricated into the walls of a trench leaving a narrowed trench into which a vertical metal-oxide-semiconductor field-effect-transistor (MOSFET) may be fabricated. One of the plates of the capacitor doubles as a source/drain layer of the transistor.

Abstract: A new method for fabricating CMOS devices, as well as the resulting devices, is disclosed. The method involves incorporating dopants into a semiconductor substrate through a region of the substrate surface, and diffusing the implanted dopants into the substrate to form a tub. Prior to the diffusion step, a trench is formed in, and extending beneath, the surface which partially or completely encircles the region. The trench serves to prevent the formation, or reduce the size, of a relatively low dopant concentration region, which would otherwise lead to undesirable leakage currents in the completed CMOS device, and prevents latchup.

Abstract: A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

Abstract: A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the device, is disclosed.The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10 .mu.m, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.

Abstract: A semiconductor integrated circuit includes a nitrided silicon dioxide layer typically 50 to 400 Angstroms thick located on a semiconductor medium. The nitrided layer is an original silicon dioxide layer that has been nitrided at its top surface, as by rapid (flash) heating in ammonia to about 1250 degrees C., in such a way that the resulting nitrided silicon dioxide layer is essentially a compound layer of silicon nitroxide on silicon dioxide in which the atomic concentration fraction of nitrogen falls from a value greater than 0.13 at the top surface of the compound layer to a value of about 0.13 within 30 Angstroms or less beneath the top surface, and advantageously to values of less than about 0.05 everywhere at distances greater than about 60 Angstroms or less beneath the top surface, except that the nitrogen fraction can rise to as much as about 0.10 in the layer at distances within about 20 Angstroms from the interface of the nitrided layer and the underlying semiconductor medium.

Abstract: A novel etchant which comprises a mixture of ethylene glycol and hydrofluoric acid, preferably buffered hydrofluoric acid, has been found to control the etch rate of refractory metal silicides, in particular titanium silicide, in a manner such that titanium silicide may be used in place of tantalum silicide for interconnects and gates in semiconductor integrated circuits.

Abstract: To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.

Abstract: A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.

Abstract: Disclosed is an eight-mask twin-tub CMOS process which forms contiguous p- and n-tubs in a relatively lightly doped bulk region in a self-aligned manner using a single masking step. The process also forms the sources and drains of the p- and n-channel transistors with a single masking step by first nonselectively implanting p-type impurities into all source and drain regions and then selectively implanting n-type impurities into only the source and drain regions of the n-channel transistors in amounts sufficient to overcompensate the p-type impurities therein.