Abstract: A system and method of detecting a fault in a transmission link are provided which includes providing a selectable reference level according to one of a direct current (DC) mode threshold and an alternating current (AC) mode threshold, wherein the DC mode threshold is a fixed potential and the AC mode threshold varies with time. An input signal arriving from the transmission link is compared to one of the DC mode threshold and the AC mode threshold to determine whether a fault is present in the transmission link.

Abstract: A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.

Abstract: A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.

Abstract: An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line.

Abstract: A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.

Abstract: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings.

Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.

Abstract: A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.

Abstract: A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

Abstract: A chip is provided in which an on-chip matching network has a first terminal conductively connected to a bond pad of the chip and a second terminal conductively connected to a common node on the chip. A wiring trace connects the on-chip matching network to a circuit of the chip. The on-chip matching network includes an electrostatic discharge protection (ESD) circuit having at least one diode having a first terminal conductively connected to the bond pad and a second terminal connected in an overvoltage discharge path to a source of fixed potential. The matching network further includes a first inductor coupled to provide a first inductive path between the bond pad and the wiring trace, a termination resistor having a first terminal connected to the common node, and a second inductor coupled to provide a second inductive path between the wiring trace and a second terminal of the termination resistor.

Abstract: A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.

Abstract: An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.

Abstract: Circuits and methods are provided for reducing the voltage stress applied to the drain to source conduction path of an FET and/or to reduce the stress to the gate oxide of an FET which may have a thin gate oxide. Thus, in a current mirror circuit disclosed herein, a first field effect transistor (FET) has a first gate and a first drain, in which the first drain is conductively connected to a current source for conducting a first current. The current mirror circuit also includes at least one second FET having a second gate conductively connected to the first gate, in which the second FET is operable to output a second current in fixed proportion to the first current. A switching element having a first conductive terminal is connected to the first gate and to the second gate, the second conductive terminal being connected to the first drain of the first FET.

Abstract: A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and transmitting the test data to a first link of the series of transmitter and receiver links, and for receiving processed test data from a last link of the series of transmitter receiver links; and at least one test transmission line for transmitting test data received by a link of the series of transmitter and receiver links to a next link of the series of transmitter and receiver links, wherein the at least one test transmission line connects the at least three transmitter and receiver links.

Abstract: A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.

Abstract: A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.

Abstract: A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.

Abstract: As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.