Patents by Inventor Luan C. Tran

Luan C. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6600190
    Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: July 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Tyler A. Lowrey, Luan C. Tran, Alan R. Reinberg, D. Mark Durcan
  • Patent number: 6589876
    Abstract: Methods of forming conductive capacitor plugs, methods of forming capacitor contact openings, and methods of forming memory arrays are described. In one embodiment, a conductive capacitor plug is formed to extend from proximate a substrate node location to a location elevationally above all conductive material of an adjacent bit line. In another embodiment, a capacitor contact opening is etched through a first insulative material received over a bit line and a word line substantially selective relative to a second insulative material covering portions of the bit line and the word line. The opening is etched to a substrate location proximate the word line in a self-aligning manner relative to both the bit line and the word line. In another embodiment, capacitor contact openings are formed to elevationally below the bit lines after the bit lines are formed. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: July 8, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 6580149
    Abstract: An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: June 17, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Mark McQueen, Robert Kerr
  • Patent number: 6579751
    Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: June 17, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Publication number: 20030095428
    Abstract: The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 22, 2003
    Inventor: Luan C. Tran
  • Publication number: 20030075810
    Abstract: Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration.
    Type: Application
    Filed: February 24, 2000
    Publication date: April 24, 2003
    Inventors: Robert Kerr, Brian Shirley, Luan C. Tran, Tyler A. Lowrey
  • Publication number: 20030073269
    Abstract: A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.
    Type: Application
    Filed: November 25, 2002
    Publication date: April 17, 2003
    Inventor: Luan C. Tran
  • Patent number: 6548390
    Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: April 15, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Pai-Hung Pan, Luan C. Tran, Tyler A. Lowrey
  • Patent number: 6545904
    Abstract: The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: April 8, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 6541362
    Abstract: One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first-layered-defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second-layer-defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: April 1, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Luan C. Tran
  • Publication number: 20030054602
    Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 20, 2003
    Inventors: Pai-Hung Pan, Luan C. Tran, Tyler A. Lowrey
  • Publication number: 20030036235
    Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.
    Type: Application
    Filed: October 3, 2002
    Publication date: February 20, 2003
    Inventor: Luan C. Tran
  • Publication number: 20030020106
    Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different.
    Type: Application
    Filed: September 1, 1999
    Publication date: January 30, 2003
    Inventor: LUAN C. TRAN
  • Publication number: 20020195626
    Abstract: An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back.
    Type: Application
    Filed: August 1, 2002
    Publication date: December 26, 2002
    Inventors: Luan C. Tran, Mark McQueen, Robert Kerr
  • Publication number: 20020195670
    Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different.
    Type: Application
    Filed: August 27, 2002
    Publication date: December 26, 2002
    Inventor: Luan C. Tran
  • Patent number: 6492693
    Abstract: A method for adjusting Vt while minimizing parasitic capacitance fiord low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: December 10, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 6489226
    Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: December 3, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Pai-Hung Pan, Luan C. Tran, Tyler A. Lowrey
  • Publication number: 20020151163
    Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
    Type: Application
    Filed: May 1, 2002
    Publication date: October 17, 2002
    Inventors: Pai-Hung Pan, Luan C. Tran, Tyler A. Lowrey
  • Patent number: 6456535
    Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: September 24, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Luan C. Tran, Alan R. Reinberg, Joseph E. Geusic, Kie Y. Ahn, Paul A. Farrar, Eugene H. Cloud, David J. McElroy
  • Patent number: 6455407
    Abstract: Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: September 24, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Pai-Hung Pan, Luan C. Tran, Tyler A. Lowrey