Abstract: An address decoder unit (30) for a memory cell array (10), the address decoder unit (30) including an address decoder (31) including an address input (33) and a number of address outputs (34, 35, 36), the address decoder (31) being operable to select one of the address outputs (34, 35, 36) in response to receive a memory address at the address input (33); and an address selection circuitry (32) connected to the address decoder (31) and including a number of address selection outputs (44, 45, 46) each of which connectable the memory cell array and each of which corresponding to one memory address, wherein the address decoder unit (30) is switchable into a memory erase mode, in which the address selection circuitry (32) is operable to select all address selection outputs (44, 45, 46) of an address space above or beyond a memory address provided at the address input (33).

Abstract: A soft switching device (sw) for connecting a power supply to at least one large electronic unit of an electronic system (1), so as to be activated via the soft switching device to the power supply. The device comprises a switch component (M1) with a control terminal and a current source (13) connected to the control terminal to control the switch component closure when the current source is activated. The soft switching device also includes a soft transition element (C1) of capacitive type between the output terminal (12) and the control terminal of the switch component (M1) so as to gradually close the switch for connection to a power supply.

Abstract: The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to t

Abstract: The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to t

Abstract: The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (VDD) and part of the circuit operates using at least one internal regulated voltage (VREG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (VDD) and earth (VSS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (Vesd). The connection device further includes switching means (3) for modifying the control signals (Vesd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (VDD) and the internal regulated voltage (VREG).

Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.

Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.

Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.

Abstract: The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Abstract: A memory circuit is provided, including at least one bit cell configured to store data and having a first terminal and a second terminal, one of the terminals being coupled to a bit-line; at least one current switch connected to the bit-line and connected to a current source and being configured to selectively provide at least a read current to the bit cell; and a sense amplifier having at least one input connected to a sensing node on the bit-line, wherein the sensing node is disposed between the bit cell and the at least one current switch.

Abstract: A fault detection assembly of an integrated circuit having a supply port, an input port and a ground port. The fault detection assembly includes a first diode connected with one end to the supply port and connected with the other end to the input port, a second diode connected with one end to the input port and connected with the other end to the ground port, at least a first fault detection transistor of MOS type. At least one of first and second diodes includes a first diode-connected MOS transistor whose gate is connected to the gate of the first fault detection transistor.

Abstract: The present invention relates to a memory circuit comprising: at least one bit cell for storing data and having a first terminal and a second terminal, wherein one of said terminals is coupled to a bit-line, at least one current switch connected to the bit-line and connected to a current source and being operable to selectively provide a current to the bit cell, a sense amplifier having at least one input connected to a sensing node on the bit-line, wherein the sensing node is located between the bit cell and the at least one current switch.

Abstract: The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: The present invention relates to a fault detection assembly of an integrated circuit having a supply port, an input port and a ground port. The fault detection assembly comprises a first diode connected with one end to the supply port and connected with the other end to the input port, a second diode connected with one end to the input port and connected with the other end to the ground port, at least a first fault detection transistor of MOS type. At least one of first and second diodes comprises a first diode-connected MOS transistor whose gate is connected to the gate of the first fault detection transistor.

Abstract: The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises: a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.

Abstract: The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (VDD) and part of the circuit operates using at least one internal regulated voltage (VREG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (VDD) and earth (VSS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (Vesd). The connection device further includes switching means (3) for modifying the control signals (Vesd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (VDD) and the internal regulated voltage (VREG).