Abstract: The integrated circuit device (1) backs up the configuration of output terminals (O, SP) of said integrated circuit in low-power mode. To do this, the device includes several voltage level shift units (2, 2?, 2?, 2??) and an output stage (3) connected to each output of the level shift units and connected to at least one external contact pad (SP) of said integrated circuit. Each level shift unit includes an input stage powered by a regulated internal voltage (VREG) and a part for transferring the state of a specific output function, which is powered by a supply voltage (VDD) of the integrated circuit. Each level shift unit also includes a memory cell at output powered by the supply voltage, for storing the output state of a specific function of the level shift unit in the idle mode of the integrated circuit where the regulated voltage is cut off.

Abstract: The integrated circuit device (1) backs up the configuration of output terminals (O, SP) of said integrated circuit in low-power mode. To do this, the device includes several voltage level shift units (2, 2?, 2?, 2??) and an output stage (3) connected to each output of the level shift units and connected to at least one external contact pad (SP) of said integrated circuit. Each level shift unit includes an input stage powered by a regulated internal voltage (VREG) and a part for transferring the state of a specific output function, which is powered by a supply voltage (VDD) of the integrated circuit. Each level shift unit also includes a memory cell at output powered by the supply voltage, for storing the output state of a specific function of the level shift unit in the idle mode of the integrated circuit where the regulated voltage is cut off.

Abstract: The invention relates to a memory device, preferably a non-volatile memory device, comprising a memory array (16) with multiple memory cells (18) for storing bits of data, the memory cells (18) being arranged in word lines and columns, and a readout circuit (20) for reading out data from the memory array (16). In order to enable an effective use of resources, it is proposed to further provide the non-volatile memory device with at least two sense amplifier devices (22, 24), wherein the sense amplifier devices (22, 24) are connected to respectively different subsets of memory cells of one of the word lines.