Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Abstract: The present invention provides a method for manufacturing micromachined devices on a substrate (10) comprising electrical circuitry, the micromachined devices comprising at least one micromachined structure, without affecting the underlying electrical circuitry. The method comprises providing a protection layer (15) on the substrate (10); providing on the protection layer (15) a plurality of patterned layers for forming the at least one micromachined structure, the plurality of patterned layers comprising at least one sacrificial layer (18); and thereafter removing at least a portion of the sacrificial layer (18) to release the at least one micromachined structure. The method furthermore comprises, before providing the protection layer (15), annealing the substrate (10) at a temperature higher than a highest temperature used during manufacturing of the micromachined device, annealing being for preventing gas formation underneath the protection layer (15) during subsequent manufacturing steps.

Abstract: The present invention includes a bimodal polyethylene polymerization process wherein metallocene catalyst to is used to adjust the hydrogen response of a Ziegler-Natta catalyst. The polymerization may be carried out in a single reactor or in two or more reactors in series, preferably two or more continuously stirred tank reactors in series. In an embodiment having two or more reactors, the Zeigler-Natta catalyst is added to a first reactor and the metallocene catalyst is added to a downstream reactor. In another embodiment having two or more reactors, the Zeigler-Natta catalyst and metallocene catalyst are added to the same reactor, preferably an upstream reactor. A preferred Zeigler-Natta catalyst comprises TiCl4, and a preferred metallocene catalyst comprises bis(cyclopentadienyl) titanium dichloride.

Abstract: The present invention relates to a method of making a multibit non-volatile memory and especially to a method of making a flash memory such as a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) device relying on hot-electron injection for programming which is particularly suited for high density low-voltage low-power applications and employs only two polysilicon layers.

Abstract: The present invention includes a bimodal polyethylene polymerization process wherein metallocene catalyst to is used to adjust the hydrogen response of a Ziegler-Natta catalyst. The polymerization may be carried out in a single reactor or in two or more reactors in series, preferably two or more continuously stirred tank reactors in series. In an embodiment having two or more reactors, the Zeigler-Natta catalyst is added to a first reactor and the metallocene catalyst is added to a downstream reactor. In another embodiment having two or more reactors, the Zeigler-Natta catalyst and metallocene catalyst are added to the same reactor, preferably an upstream reactor. A preferred Zeigler-Natta catalyst comprises TiCl4, and a preferred metallocene catalyst comprises bis(cyclopentadienyl) titanium dichloride.

Abstract: The present invention relates to a method of making a multibit non-volatile memory and especially to a method of making a flash memory such as a fast-programmable Flash EEPROM (Electrically Erasable Programmable Read-Only Memory) device relying on hot-electron injection for programming which is particularly suited for high density low-voltage low-power applications and employs only two polysilicon layers.

Abstract: A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.

Abstract: The present invention is related to a method for producing micromachined devices for use in Microelectromechanical Systems (MEMS), comprising the steps of providing a crystalline wafer, and processing from said wafer at least one micromachined device comprising at least one elongated opening and/or cavity, having a longitudinal axis, so that said longitudinal axis is at an angle to a direction which lies along the intersection of the front plane of the wafer and a cleavage plane, said cleavage plane being defined as a plane along which cleavage of the wafer is most likely to occur.

Abstract: The present invention includes a bimodal polyethylene polymerization process wherein metallocene catalyst to is used to adjust the hydrogen response of a Ziegler-Natta catalyst. The polymerization may be carried out in a single reactor or in two or more reactors in series, preferably two or more continuously stirred tank reactors in series. In an embodiment having two or more reactors, the Zeigler-Natta catalyst is added to a first reactor and the metallocene catalyst is added to a downstream reactor. In another embodiment having two or more reactors, the Zeigler-Natta catalyst and metallocene catalyst are added to the same reactor, preferably an upstream reactor. A preferred Zeigler-Natta catalyst comprises TiCl4, and a preferred metallocene catalyst comprises bis(cyclopentadienyl) titanium dichloride.

Abstract: A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline.

Abstract: The present invention includes a bimodal polyethylene polymerization process wherein metallocene catalyst to is used to adjust the hydrogen response of a Ziegler-Natta catalyst. The polymerization may be carried out in a single reactor or in two or more reactors in series, preferably two or more continuously stirred tank reactors in series. In an embodiment having two or more reactors, the Zeigler-Natta catalyst is added to a first reactor and the metallocene catalyst is added to a downstream reactor. In another embodiment having two or more reactors, the Zeigler-Natta catalyst and metallocene catalyst are added to the same reactor, preferably an upstream reactor. A preferred Zeigler-Natta catalyst comprises TiCl4, and a preferred metallocene catalyst comprises bis(cyclopentadienyl) titanium dichloride.

Abstract: A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Source and drain regions are formed self-aligned to the outer borders of this memory structure. Depending on the biasing scheme a poly line is used as the select gate of the memory cell while an adjacent poly line is used as program gate, so to have charge stored underneath this adjacent poly line using source-side-injection of charge carriers. The other poly lines are biased to form conductive channels between the select and program gate to the source and drain regions. These conductive channels form soft source and drain regions next to the select and program gate in use.

Abstract: A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Source and drain regions are formed self-aligned to the outer borders of this memory structure. Depending on the biasing scheme a poly line is used as the select gate of the memory cell while an adjacent poly line is used as program gate, so to have charge stored underneath this adjacent poly line using source-side-injection of charge carriers. The other poly lines are biased to form conductive channels between the select and program gate to the source and drain regions. These conductive channels form soft source and drain regions next to the select and program gate in use.

Abstract: A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Source and drain regions are formed self-aligned to the outer borders of this memory structure. Depending on the biasing scheme a poly line is used as the select gate of the memory cell while an adjacent poly line is used as program gate, so to have charge stored underneath this adjacent poly line using source-side-injection of charge carriers. The other poly lines are biased to form conductive channels between the select and program gate to the source and drain regions. These conductive channels form soft source and drain regions next to the select and program gate in use.

Abstract: The present invention is related to a method for producing micromachined devices for use in Microelectromechanical Systems (MEMS), comprising the steps of providing a crystalline wafer, and processing from said wafer at least one micromachined device comprising at least one elongated opening and/or cavity, having a longitudinal axis, so that said longitudinal axis is at an angle to a direction which lies along the intersection of the front plane of the wafer and a cleavage plane, said cleavage plane being defined as a plane along which cleavage of the wafer is most likely to occur.

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.

Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.

Abstract: Olefin polymers and copolymers having controlled morphology are prepared by bulk or slurry polymerization using metallocene catalysts in the presence of an alumoxane cocatalyst. Prepolymerization at a temperature of -10.degree. C. to +35.degree. C. during 1.5 to 3.5 minutes is immediately followed by polymerization at 55.degree.-70.degree. C.The fluff has a narrow grain size distribution, a smooth surface and a high bulk density.