Patents by Inventor Luca Fasoli

Luca Fasoli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868672
    Abstract: A user device can verify a user's identity to a server while protecting user privacy by not sharing any personal data with any other device. To ensure user privacy and to allow multiple independent enrollments, the user device performs an enrollment process in which the user device locally collects and uses biometric data together with a random salt to generate a set of public/private key pairs from which biometric information cannot be extracted. The public keys and the salt, but not the biometric data, are sent to a server to store. To verify user identity, a user device can repeat the collection of biometric data from the user and the generation of public/private key pairs using the salt obtained from the server. If the device can prove to the server its possession of at least a minimum number of correct private keys, the user's identity can be verified.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Apple Inc.
    Inventors: Augustin J. Farrugia, Ritwik K. Kumar, Gianpaolo Fasoli, Mathieu Ciet, Bruno Kindarji, Eric D. Friedman, Gianluca Barbieri, Lucas O. Winstrom
  • Patent number: 10599873
    Abstract: Systems and methods are described for rate-limiting a message-sending client interacting with a message service based on dynamically calculated risk assessments of the probability that the client is, or is not, a sender of a spam messages. The message service sends a proof of work problem to a sending client device with a difficulty level that is related to a risk assessment that the client is a sender of spam messages. The message system limits the rate at which a known or suspected spammer can send messages by giving the known or suspected spammer client harder proof of work problems to solve, while minimizing the burden on normal users of the message system by given them easier proof of work problems to solve that can typically be solved by the client within the time that it takes to type a message.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 24, 2020
    Assignee: Apple Inc.
    Inventors: Lucas O. Winstrom, Eric D. Friedman, Ritwik K. Kumar, Jeremy M. Stober, Amol V. Pattekar, Benoit Chevallier-Mames, Julien Lerouge, Gianpaolo Fasoli, Augustin J. Farrugia, Mathieu Ciet
  • Patent number: 9245629
    Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: January 26, 2016
    Assignee: SANDISK 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Masaaki Higashitani, Roy Edwin Scheuerlein
  • Patent number: 9105576
    Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: August 11, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein, Luca Fasoli
  • Patent number: 8982597
    Abstract: The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: March 17, 2015
    Assignee: Sandisk 3D LLC
    Inventors: Tianhong Yan, Luca Fasoli
  • Patent number: 8913413
    Abstract: The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: December 16, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Tianhong Yan, Luca Fasoli
  • Publication number: 20140346433
    Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Inventors: Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein, Luca Fasoli
  • Patent number: 8841648
    Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: September 23, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein, Luca Fasoli
  • Patent number: 8824191
    Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 2, 2014
    Assignee: Sandisk 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Yan Li, Tianhong Yan
  • Patent number: 8780651
    Abstract: A system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 15, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Tianhong Yan, Luca Fasoli
  • Patent number: 8711596
    Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 29, 2014
    Assignee: Sandisk 3D LLC
    Inventors: Tianhong Yan, Luca Fasoli
  • Publication number: 20140043911
    Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
    Type: Application
    Filed: October 18, 2013
    Publication date: February 13, 2014
    Applicant: SANDISK 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Masaaki Higashitani, Roy Edwin Scheuerlein
  • Patent number: 8638586
    Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 28, 2014
    Assignee: Sandisk 3D LLC
    Inventors: Tianhong Yan, Luca Fasoli
  • Publication number: 20140022848
    Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
    Type: Application
    Filed: August 22, 2013
    Publication date: January 23, 2014
    Applicant: SANDISK 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Yan Li, Tianhong Yan
  • Patent number: 8547720
    Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: October 1, 2013
    Assignee: Sandisk 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Masaaki Higashitani, Roy Edwin Scheuerlein
  • Patent number: 8526237
    Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: September 3, 2013
    Assignee: SanDisk 3D LLC
    Inventors: George Samachisa, Luca Fasoli, Yan Li, Tianhong Yan
  • Patent number: 8427890
    Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: April 23, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Gopinath Balakrishnan, Luca Fasoli, Tz-Yi Liu, Yuheng Zhang, Yan Li
  • Patent number: 8395948
    Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: March 12, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Gopinath Balakrishnan, Luca Fasoli, Tz-Yi Liu, Yuheng Zhang, Yan Li
  • Patent number: RE46154
    Abstract: A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: September 20, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Luca Fasoli, Yuheng Zhang, Gopinath Balakrishnan
  • Patent number: RE46348
    Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Gopinath Balakrishnan, Luca Fasoli, Tz-Yi Liu, Yuheng Zhang, Yan Li