Patents by Inventor Luca Pividori
Luca Pividori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10109590Abstract: A method for indexing electronic devices includes: forming first chips in a first wafer, forming second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device. The index is indicative of a position of the corresponding first chip in the first wafer. The step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.Type: GrantFiled: June 25, 2015Date of Patent: October 23, 2018Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Freguglia, Luca Pividori
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Publication number: 20150294942Abstract: A method for indexing electronic devices includes: forming first chips in a first wafer, forming second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device. The index is indicative of a position of the corresponding first chip in the first wafer. The step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.Type: ApplicationFiled: June 25, 2015Publication date: October 15, 2015Applicant: STMicroelectronics S.r.l.Inventors: Alessandro Freguglia, Luca Pividori
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Patent number: 9099480Abstract: An embodiment of a method is proposed for indexing electronic devices. The embodiment includes the steps of forming a plurality of first chips in a first wafer, forming a plurality of second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device; the index is indicative of a position of the corresponding first chip in the first wafer. In an embodiment, the step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.Type: GrantFiled: September 30, 2010Date of Patent: August 4, 2015Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Freguglia, Luca Pividori
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Publication number: 20110073966Abstract: An embodiment of a method is proposed for indexing electronic devices. The embodiment includes the steps of forming a plurality of first chips in a first wafer, forming a plurality of second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device; the index is indicative of a position of the corresponding first chip in the first wafer. In an embodiment, the step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.Type: ApplicationFiled: September 30, 2010Publication date: March 31, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Alessandro FREGUGLIA, Luca PIVIDORI
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Patent number: 7220686Abstract: A method is provided for contact opening definition for active element electrical connections. According to the method, a layer of BPSG is formed on a surface of an integrated circuit, and a transparent layer of nitride UV is formed above the layer of BPSG. Preferably, the transparent layer of nitride UV is formed by deposition using an HDP process and has a thickness of less than about 500 ?. In one embodiment, after forming a transparent layer of nitride UV, two overlapped layers of BARC and resist are formed on the surface of the integrated circuit. Also provided is a machine-readable medium encoded with a program for contact opening definition for active element electrical connections.Type: GrantFiled: September 12, 2003Date of Patent: May 22, 2007Assignee: STMicroelectronics S.r.l.Inventor: Luca Pividori
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Publication number: 20070105314Abstract: A non volatile memory device is integrated on a semiconductor substrate and includes a matrix of memory cells with an associated circuitry. The process for forming the memory device includes forming in the semiconductor substrate first dielectric insulation regions of the matrix to define and insulate first active areas of the matrix from each other, and forming in the semiconductor substrate second dielectric insulation regions of the associated circuitry to define and insulate second active areas of the circuitry from each other. At least one dielectric layer is formed on the first and second active areas. A first conductive layer is deposited on the whole device, and floating gate electrodes of the memory cells of the matrix are defined in the first conductive layer, with the first conductive layer being removed from the associated circuitry.Type: ApplicationFiled: September 27, 2006Publication date: May 10, 2007Applicant: STMicroelectronics S.r.l.Inventors: Luca Pividori, Claudio Crippa
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Patent number: 7192820Abstract: A method for reducing non-uniformity or topography variation between a cell array area and a peripheral circuitry area is used in a process for manufacturing semiconductor integrated non-volatile memory devices, wherein an intermediate stack of multiple layers is provided during the manufacturing steps of gates structures in both the array and circuitry areas. A thin stack comprising at least a thin dielectric layer and a third conductive layer is provided over a second conductive layer before the step of defining the control gate structures in the array and the single gates in the peripheral circuitry. This intermediate stack of multiple layers is used in order to compensate for thickness differences between the dual gate structures in the array and the single gate transistors in the peripheral circuitry.Type: GrantFiled: February 16, 2005Date of Patent: March 20, 2007Assignee: STMicroelectronics S.R.L.Inventor: Luca Pividori
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Publication number: 20060148173Abstract: The method is for manufacturing electronic memory devices on a semiconductor substrate including a non-volatile memory matrix and associated circuitry. The method includes forming a first insulation layer, a conductive layer and a second insulation layer. A resist mask is formed corresponding with the memory matrix to define a predetermined geometry in the second insulation layer. The exposed portions of the second insulation layer are isotropically etched. Also, a conformal protective layer is formed and removed via a second highly selective etching step to form portions of the conformal protective layer on side walls of the resist mask and of the insulation layer. A third isotropic etching step removes the insulation layers left exposed by the resist mask and by the portions of the protective layer. The portions of the conformal protective layer and of the resist mask are then removed.Type: ApplicationFiled: December 14, 2005Publication date: July 6, 2006Applicant: STMicroelectronics S.r.l.Inventor: Luca Pividori
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Publication number: 20050185446Abstract: A method for reducing non-uniformity or topography variation between a cell array area and a peripheral circuitry area is used in a process for manufacturing semiconductor integrated non-volatile memory devices, wherein an intermediate stack of multiple layers is provided during the manufacturing steps of gates structures in both the array and circuitry areas. A thin stack comprising at least a thin dielectric layer and a third conductive layer is provided over a second conductive layer before the step of defining the control gate structures in the array and the single gates in the peripheral circuitry. This intermediate stack of multiple layers is used in order to compensate for thickness differences between the dual gate structures in the array and the single gate transistors in the peripheral circuitry.Type: ApplicationFiled: February 16, 2005Publication date: August 25, 2005Inventor: Luca Pividori
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Patent number: 6812098Abstract: A method of manufacturing a non-volatile memory device includes depositing a first layer on a semiconductor substrate, and a portion of the first layer is selectively removed to form a memory array area. A second layer is deposited on the memory array area and on adjacent areas of the semiconductor substrate contacting the memory array area. The second layer has a thickness that is substantially equal over the memory array area and over the adjacent areas. The method further includes forming a screening layer on the second layer on the adjacent areas except for outer peripheral portions thereof adjacent the memory array area. The thickness of the second layer exposed on the memory array area and on the outer peripheral portions of the adjacent areas is reduced so that a resulting thickness is less than a thickness of the first layer.Type: GrantFiled: May 15, 2003Date of Patent: November 2, 2004Assignee: STMicroelectronics S.r.l.Inventors: Luca Pividori, Carmen Calareso
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Publication number: 20040121589Abstract: A method is provided for contact opening definition for active element electrical connections. According to the method, a layer of BPSG is formed on a surface of an integrated circuit, and a transparent layer of nitride UV is formed above the layer of BPSG. Preferably, the transparent layer of nitride UV is formed by deposition using an HDP process and has a thickness of less than about 500 Å. In one embodiment, after forming a transparent layer of nitride UV, two overlapped layers of BARC and resist are formed on the surface of the integrated circuit. Also provided is a machine-readable medium encoded with a program for contact opening definition for active element electrical connections.Type: ApplicationFiled: September 12, 2003Publication date: June 24, 2004Applicant: STMICROELECTRONICS S.r.l.Inventor: Luca Pividori
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Publication number: 20040002192Abstract: A method of manufacturing a non-volatile memory device includes depositing a first layer on a semiconductor substrate, and a portion of the first layer is selectively removed to form a memory array area. A second layer is deposited on the memory array area and on adjacent areas of the semiconductor substrate contacting the memory array area. The second layer has a thickness that is substantially equal over the memory array area and over the adjacent areas. The method further includes forming a screening layer on the second layer on the adjacent areas except for outer peripheral portions thereof adjacent the memory array area. The thickness of the second layer exposed on the memory array area and on the outer peripheral portions of the adjacent areas is reduced so that a resulting thickness is less than a thickness of the first layer.Type: ApplicationFiled: May 15, 2003Publication date: January 1, 2004Applicant: STMicroelectronics S.r.l.Inventors: Luca Pividori, Carmen Calareso
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Patent number: 6630739Abstract: A method of depositing a dielectric ply structure to optimize the planarity of electronic devices that include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. In accordance with the principles of the present invention, the plurality of bit lines may be isolated from one another by the dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited. The resulting planarization avoids the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces upon which the conductive layer is deposited.Type: GrantFiled: October 13, 2000Date of Patent: October 7, 2003Assignee: STMicroelectronics S.r.l.Inventors: Patrizia Sonego, Elio Colabella, Maurizio Bacchetta, Luca Pividori
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Patent number: 6602774Abstract: A selective silicidation process for electronic devices that are integrated on a semiconductor substrate is presented. The devices have a number of active elements formed with gate region that has at least one polysilicon layer. The process begins with depositing a dielectric layer over the entire surface of the semiconductor. Then portions of the dielectric layer are removed to expose the polysilicon layer in the gate regions. Next, a layer of a transition metal is deposited and subjected to a thermal treatment for selectively reacting it with the polysilicon layers and producing a silicide layer over the gate regions.Type: GrantFiled: December 28, 1999Date of Patent: August 5, 2003Assignee: STMicroelectronics S.r.l.Inventors: Gabriella Fontana, Luca Pividori
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Patent number: 6586313Abstract: Method for fabricating integrated circuits comprising non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of preparing a silicon substrate, carrying out a shallow trench isolation process on the silicon substrate to form active areas of exposed silicon isolated from one another by trenches filled with field oxide, growing a thin oxide layer on the active areas, masking the substrate areas intended for the memory cell matrices and etching the thin oxide layer and the field oxide by a chemical etch for a time longer than the time needed for removing the thin oxide layer entirely from the substrate areas intended for the peripheral circuits.Type: GrantFiled: November 29, 2001Date of Patent: July 1, 2003Assignee: STMicroelectronics S.r.l.Inventor: Luca Pividori
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Publication number: 20030100166Abstract: Method for fabricating integrated circuits comprising non-volatile memory cell matrices and peripheral circuits, said method comprising the steps of preparing a silicon substrate, carrying out a shallow trench isolation process on the silicon substrate to form active areas of exposed silicon isolated from one another by trenches filled with field oxide, growing a thin oxide layer on the active areas, masking the substrate areas intended for the memory cell matrices and etching the thin oxide layer and the field oxide by a chemical etch for a time longer than the time needed for removing the thin oxide layer entirely from the substrate areas intended for the peripheral circuits.Type: ApplicationFiled: November 29, 2001Publication date: May 29, 2003Applicant: STMicroelectronics S.r.l.Inventor: Luca Pividori
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Publication number: 20030030130Abstract: A semiconductor device including an electronic component and an edge region delimited by a side surface. The device is formed in a substrate of semiconductor material overlaid by a plurality of superficial layers which form, on top of the edge region, a stack of insulating layers. A first groove extends in the stack of insulating layers near the electronic component. A second groove extends in the stack of insulating layers between the first groove and the side surface and operates as an element of mechanical decoupling which blocks any possible delayering of the superficial layers during cutting of the wafer.Type: ApplicationFiled: July 29, 2002Publication date: February 13, 2003Applicant: STMicroelectronics S.r.I.Inventor: Luca Pividori
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Patent number: 6458659Abstract: A method of fabricating non-volatile memory devices integrated in a semiconductor substrate is presented. The memory devices include a matrix of non-volatile memory cells, each having floating-gate MOS transistors with associated gate electrodes, as well as control circuitry formed of MOS transistors also having gate electrodes. The method includes forming gate electrodes above the substrate, then depositing a first dielectric layer onto the entire exposed surface. Next the first dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the matrix cells. Then a second dielectric layer is deposited onto the entire exposed surface, and the memory matrix is overlaid with a protective layer. In the circuitry area, the second dielectric layer is etched back to form isolating spacers on the side walls of the gate electrodes of the circuitry transistors, while the floating-gate MOS transistors are protected.Type: GrantFiled: May 19, 2000Date of Patent: October 1, 2002Assignee: STMicroelectronics, S.r.l.Inventors: Luca Pividori, Lidia Brusaferri
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Patent number: 6380582Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.Type: GrantFiled: March 17, 2000Date of Patent: April 30, 2002Assignee: STMicroelectronics S.r.l.Inventors: Emilio Camerlenghi, Elio Colabella, Luca Pividori, Adriana Rebora
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Publication number: 20020014653Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.Type: ApplicationFiled: March 17, 2000Publication date: February 7, 2002Inventors: Emilo Camerlenghi, Elio Colabella, Luca Pividori, Adriana Rebora