Patents by Inventor Lucas Porzio
Lucas Porzio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190012173Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: ApplicationFiled: August 20, 2018Publication date: January 10, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Kindworth
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Patent number: 10163472Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.Type: GrantFiled: July 6, 2017Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio
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Publication number: 20180349302Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.Type: ApplicationFiled: August 8, 2018Publication date: December 6, 2018Applicant: Micron Technology, Inc.Inventors: Graziano Mirichigni, Daniele Balluchi, Luca Porzio
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Patent number: 10108372Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.Type: GrantFiled: January 26, 2015Date of Patent: October 23, 2018Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio, Antonino Pollio
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Patent number: 10067764Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: GrantFiled: July 11, 2017Date of Patent: September 4, 2018Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Patent number: 10067890Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.Type: GrantFiled: August 2, 2017Date of Patent: September 4, 2018Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Daniele Balluchi, Luca Porzio
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Patent number: 9977603Abstract: A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to detect a known state to enter based, at least in part, on communication with a host device, and reconfigure the memory device to prepare for the known state. A host controller is configured to communicate with the memory device to support a feature and protocol for detecting the known state for operation of the memory device. Related methods and systems are also disclosed.Type: GrantFiled: May 2, 2016Date of Patent: May 22, 2018Assignee: Micron Technology, Inc.Inventors: Luca Porzio, Graziano Mirichigni, Danilo Caraccio
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Publication number: 20180121356Abstract: Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: ApplicationFiled: December 28, 2017Publication date: May 3, 2018Applicant: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Patent number: 9928171Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: GrantFiled: June 29, 2017Date of Patent: March 27, 2018Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Publication number: 20180039572Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.Type: ApplicationFiled: October 17, 2017Publication date: February 8, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Graziano Mirichigni, Danilo Caraccio, Luca Porzio
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Patent number: 9852781Abstract: An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the matrix into a plurality of subspaces; each subspace comprises at least one respective memory cell. The memory device further comprises selection means for selecting a subspace, operative means for performing an operation on all the memory cells of the selected subspace, and means for dynamically modifying the number of subspaces and/or the number of memory cells included in each subspace.Type: GrantFiled: February 10, 2010Date of Patent: December 26, 2017Assignee: STMICROELECTRONICS S.R.L.Inventors: Emanuele Confalonieri, Giuseppe Russo, Luca Porzio
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Patent number: 9824004Abstract: Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the memory. The host is configured to provide a plurality of memory access requests to the memory, to request ready status information regarding whether the memory is ready to execute a memory access request of the plurality of memory access requests, and to request execution of the memory access request responsive to the ready status information.Type: GrantFiled: October 3, 2014Date of Patent: November 21, 2017Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Danilo Caraccio, Luca Porzio
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Publication number: 20170329534Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.Type: ApplicationFiled: August 2, 2017Publication date: November 16, 2017Applicant: Micron Technology, Inc.Inventors: Graziano Mirichigni, Daniele Balluchi, Luca Porzio
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Publication number: 20170315734Abstract: A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to detect a known state to enter based, at least in part, on communication with a host device, and reconfigure the memory device to prepare for the known state. A host controller is configured to communicate with the memory device to support a feature and protocol for detecting the known state for operation of the memory device. Related methods and systems are also disclosed.Type: ApplicationFiled: May 2, 2016Publication date: November 2, 2017Inventors: Luca Porzio, Graziano Mirichigni, Danilo Caraccio
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Publication number: 20170308382Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: ApplicationFiled: July 11, 2017Publication date: October 26, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Publication number: 20170309318Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.Type: ApplicationFiled: July 6, 2017Publication date: October 26, 2017Applicant: MICRON TECHNOLOGY INC.Inventors: GRAZIANO MIRICHIGNI, Corrado Villa, Luca Porzio
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Publication number: 20170300413Abstract: Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.Type: ApplicationFiled: June 29, 2017Publication date: October 19, 2017Applicant: Micron Technology, Inc.Inventors: Graziano Mirichigni, Luca Porzio, Erminio Di Martino, Giacomo Bernardi, Domenico Monteleone, Stefano Zanardi, Chee Weng Tan, Sebastien LeMarie, Andre Klindworth
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Patent number: 9754648Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.Type: GrantFiled: March 11, 2013Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio
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Patent number: 9740485Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.Type: GrantFiled: March 15, 2013Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Corrado Villa, Luca Porzio, Chee Weng Tan, Sebastien Lemarie, Andre Klindworth
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Patent number: 9734097Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.Type: GrantFiled: March 15, 2013Date of Patent: August 15, 2017Assignee: Micron Technology, Inc.Inventors: Graziano Mirichigni, Daniele Balluchi, Luca Porzio