Abstract: A fully digital synthesizable digital controller (152, 152a) controls a switch-mode DC-DC converter (150, 230, 240, 250, 260) having switching elements (154) and an LC circuit (156, 157) for producing an output voltage (160) that is maintained at a desired level regardless of load changes that can occur on the output. The digital controller (152, 152a) comprises an input stage (164), proportional-integral-derivative (PID) compensator (170), and a digital sigma-delta modulator (172). The input stage (164) produces a difference signal between a reference voltage Vref and a feedback voltage Vfbk, and comprises (i) first and second delta-sigma-delta modulators (178, 180) and a subtractor (182), (ii) a delta-sigma-delta modulator (180) and a subtractor (182); or (iii) a comparator (218). The PID compensator (170) processes the difference signal to compensate for an undesired phase shift and to stabilize the feedback loop.

Abstract: A fully digital synthesizable digital controller (152,152a) controls a switch-mode DC-DC converter (150,230,240,250,260) having switching elements (154) and an LC circuit (156,157) for producing an output voltage (160) that is maintained at a desired level regardless of load changes that can occur on the output. The digital controller (152,152a) comprises an input stage (164), proportional-integral-derivative (PID) compensator (170), and a digital sigma-delta modulator (172). The input stage (164) produces a difference signal between a reference voltage Vref and a feedback voltage Vfbk, and comprises (i) first and second delta-sigma-delta modulators (178,180) and a subtractor (182), (ii) a delta-sigma-delta modulator (180) and a subtractor (182); or (iii) a comparator (218). The PID compensator (170) processes the difference signal to compensate for an undesired phase shift and to stabilize the feedback loop.

Abstract: An Analog-to-Digital Converter (ADC) is provided. An embodiment of the ADC includes a modified Delta modulator including a digital feedback loop, and a digital Sigma-Delta modulator configured within the feedback loop. Embodiments of the invention provide analog functionality with all the benefits of a digital design process as well as various other advantages provided by a Delta-Sigma-Delta modulator configuration.

Abstract: An Analog-to-Digital Converter (ADC) is provided. An embodiment of the ADC includes a modified Delta modulator including a digital feedback loop, and a digital Sigma-Delta modulator configured within the feedback loop. Embodiments of the invention provide analog functionality with all the benefits of a digital design process as well as various other advantages provided by a Delta-Sigma-Delta modulator configuration.

Abstract: An embodiment of a self-aligning resonator filter circuit includes a tunable resonator having a filter output node, an oscillator having an oscillator output node, a resistance element connected between the oscillator output node and the filter output node when the self-aligning resonator filter circuit is in a tuning mode, and a phase detector loop controller coupled between the oscillator output node and the filter output node. The phase detector loop controller is configured to measure a phase difference across the resistance element, and to adjust the tunable resonator in response to the phase difference.

Abstract: A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and B-channel data of a previous frame are read from a second memory at a second clock rate and in a manner for interleaving the previous frame companded A-channel and B-channel data into the NICAM standard required interleaved format, wherein the companded A-channel and B-channel data of the previous frame was temporarily stored during a previous frame into the second memory in a format other than an interleaved format according to NICAM standard requirements.

Abstract: A NICAM encoding method comprises performing NICAM processing and coupling a front-end to the NICAM processing. The front-end processing operates with a system clock that is integer divisible such that the system clock can be used by both the NICAM processing and the front-end processing. The front-end processing includes a front-end input processing and a front-end output processing. The front-end input processing is coupled to an input of the NICAM processing and the front-end output processing is coupled to an output of the NICAM processing.

Abstract: An embodiment of a self-aligning resonator filter circuit includes a tunable resonator having a filter output node, an oscillator having an oscillator output node, a resistance element connected between the oscillator output node and the filter output node when the self-aligning resonator filter circuit is in a tuning mode, and a phase detector loop controller coupled between the oscillator output node and the filter output node. The phase detector loop controller is configured to measure a phase difference across the resistance element, and to adjust the tunable resonator in response to the phase difference.

Abstract: A self-aligning resonator filter, a self-aligning coupled resonator filter circuit, and a television tuner circuit incorporating the filter and the circuit are disclosed herein. The self-aligning resonator filter leverages the local oscillator of the tuner circuit and can be realized with a significant reduction in the amount of off-chip components. The self-aligning resonator filter is configured to align its tunable resonator to resonate at a desired frequency in response to a phase difference measured across a resistance element during a tuning mode, and the resistance element is switched out of the self-aligning resonator filter during a run mode. The self-aligning coupled resonator filter circuit is configured to isolate its individual resonator stages during tuning such that each resonator stage can be aligned without being influenced by the other resonator stage.

Abstract: A BTSC encoder includes dual channel ADC, sync separator, audio processor, filtering device, and a composite audio signal generating device. The filtering device includes a first filter for providing a filtered L+R signal, and a second filter for providing at least one of: i) a filtered and combined pilot and modulated L?R signal and ii) separately filtered pilot and modulated L?R signals. The composite audio signal generating device is responsive to the filtered L+R signal, and at least one of i) the filtered and combined pilot and modulated L?R signal and ii) the separately filtered pilot and modulated L?R signals for generating and outputting a composite analog audio signal. In all embodiments, the modulated L?R signal is filtered via an anti-splatter filter.

Abstract: A circuit for performing an arithmetic function on a number performs the function using successive approximation. Each approximation produces an estimate of the result. A determination of the utility of this estimate is made by comparing the inverse function of a given estimate to the number. The current estimate is updated based on this comparison and the inverse function of the current estimate is stored. The next estimate is an incremental change from the previous estimate and there is a corresponding incremental change in the inverse function from the current estimate to the next estimate. Rather than calculating the whole inverse function, which would typically require a multiplier, only the incremental change in the inverse function is provided simply. The incremental change in the inverse function is then added to the inverse function of the current estimate and compared to the number for determining the utility of the next estimate.

Abstract: A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134).

Abstract: An RF carrier generator comprises a circuit for sequentially counting as a function of a randomized offset and time interval, and a memory coupled to the sequential counting circuit. The memory stores samples of a desired Sigma-Delta modulator sequence bit stream. Responsive to an output of the sequential counting circuit, the memory sequentially outputs a single-bit output bit stream of a series of partial sequences of the desired Sigma-Delta modulator sequence bit stream. A method is also disclosed.

Abstract: An RF carrier generator comprises a circuit for sequentially counting as a function of a randomized offset and time interval, and a memory coupled to the sequential counting circuit. The memory stores samples of a desired Sigma-Delta modulator sequence bit stream. Responsive to an output of the sequential counting circuit, the memory sequentially outputs a single-bit output bit stream of a series of partial sequences of the desired Sigma-Delta modulator sequence bit stream. A method is also disclosed.

Abstract: A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and B-channel data of a previous frame are read from a second memory at a second clock rate and in a manner for interleaving the previous frame companded A-channel and B-channel data into the NICAM standard required interleaved format, wherein the companded A-channel and B-channel data of the previous frame was temporarily stored during a previous frame into the second memory in a format other than an interleaved format according to NICAM standard requirements.

Abstract: A NICAM processor comprises a first memory for temporarily storing a current frame of A-channel and B-channel input data, wherein the current frame data is stored into the first memory at a first clock rate. A second memory temporarily stores companded A-channel and B-channel data of a previous frame in a format other than an interleaved format according to NICAM standard requirements. An interleaving circuit reads the previous frame companded data from the second memory at a second clock rate and in a manner for interleaving the previous frame data into the NICAM standard required interleaved format. A bit stream generator generates a first portion of an output bit stream, multiplexes it with a payload portion, and outputs the output bit stream, wherein the first portion comprises a frame alignment word, control information and additional data, and the payload portion comprises the interleaved data of the previous frame.

Abstract: A self-aligning resonator filter, a self-aligning coupled resonator filter circuit, and a television tuner circuit incorporating the filter and the circuit are disclosed herein. The self-aligning resonator filter leverages the local oscillator of the tuner circuit and can be realized with a significant reduction in the amount of off-chip components. The self-aligning resonator filter is configured to align its tunable resonator to resonate at a desired frequency in response to a phase difference measured across a resistance element during a tuning mode, and the resistance element is switched out of the self-aligning resonator filter during a run mode. The self-aligning coupled resonator filter circuit is configured to isolate its individual resonator stages during tuning such that each resonator stage can be aligned without being influenced by the other resonator stage.

Abstract: A NICAM encoding method comprises performing NICAM processing and coupling a front-end to the NICAM processing. The front-end processing operates with a system clock (68) that is integer divisible such that the system clock can be used by both the NICAM processing and the front-end processing.

Abstract: A variable interpolator (110) has an interpolation factor L for performing an interpolation of an input signal (124), where L is variable and includes a minimum value. The variable interpolator includes a differentiator (110-1), a chopper (112), and an integrator (110-2). The differentiator (110-1) is responsive to a signal on the differentiator input for performing a differentiator portion of the interpolation and for providing a differentiator result signal (134).

Abstract: A NICAM encoder (54) comprises a NICAM processor (82) and a front-end section (80,84) coupled to the NICAM processor. The front-end section is configured for operating with a system clock (68) that is integer divisible such that the system clock can be used by both the NICAM processor (82) and the front-end section (80,84).