Patents by Inventor Lucio Lanza

Lucio Lanza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11775722
    Abstract: Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: October 3, 2023
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 11748541
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: September 5, 2023
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20220277126
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 11301609
    Abstract: Systems and methods for managing operations for generating a plurality of designs of an integrated circuit chip are described. One of the methods includes receiving a request with a specification of the integrated circuit chip from a requester account, receiving a plurality of requests from a plurality of community member accounts for viewing the specification, and providing access to the specification to the plurality of community member accounts. The method further includes receiving a plurality of instances of the acceptance from the plurality of community member accounts for creating the plurality of designs, providing access to a plurality of resources to the plurality of community member accounts, and receiving a plurality of design files having the plurality of designs from the plurality of community member accounts. The method includes providing access to the plurality of designs to the requester account for approval or disapproval of the plurality of designs.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: April 12, 2022
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20220043956
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20220027544
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 11182526
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 23, 2021
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20200285795
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 10671700
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 2, 2020
    Assignee: efavless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20200089833
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 19, 2020
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20190392105
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Application
    Filed: September 9, 2019
    Publication date: December 26, 2019
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 10452802
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 22, 2019
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 10437953
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 8, 2019
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Patent number: 10423748
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: September 24, 2019
    Assignee: efabless corporation
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20180011948
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Application
    Filed: June 26, 2017
    Publication date: January 11, 2018
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20180011958
    Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.
    Type: Application
    Filed: June 26, 2017
    Publication date: January 11, 2018
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20180011959
    Abstract: Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.
    Type: Application
    Filed: June 26, 2017
    Publication date: January 11, 2018
    Inventors: Bertrand Irissou, John M. Hughes, Lucio Lanza, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava, Risto Bell, Robert Timothy Edwards, Sherif Eid, Greg P. Shaurette
  • Publication number: 20080098334
    Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
    Type: Application
    Filed: October 2, 2007
    Publication date: April 24, 2008
    Inventors: Lawrence Pileggi, Andrzej Strojwas, Lucio Lanza
  • Patent number: 7191413
    Abstract: A method and apparatus for thermal testing of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and positioning temperature sensors within a corresponding semiconductor chip in accordance with the calculated full-chip temperatures (e.g., in the regions of steep thermal gradients). Thus, temperature sensors are strategically placed in the regions where they are most likely to be needed, according to calculated temperatures, rather than randomly positioned throughout a test chip.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: March 13, 2007
    Assignee: Gradient Design Automation, Inc.
    Inventors: Rajit Chandra, Lucio Lanza
  • Publication number: 20060112355
    Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.
    Type: Application
    Filed: November 4, 2005
    Publication date: May 25, 2006
    Applicant: Fabbrix, Inc.
    Inventors: Lawrence Pileggi, Andrzej Strojwas, Lucio Lanza