Patents by Inventor Lucio Lanza

Lucio Lanza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050166166
    Abstract: A method and apparatus for thermal testing of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and positioning temperature sensors within a corresponding semiconductor chip in accordance with the calculated full-chip temperatures (e.g., in the regions of steep thermal gradients). Thus, temperature sensors are strategically placed in the regions where they are most likely to be needed, according to calculated temperatures, rather than randomly positioned throughout a test chip.
    Type: Application
    Filed: March 11, 2005
    Publication date: July 28, 2005
    Inventors: Rajit Chandra, Lucio Lanza
  • Patent number: 4156290
    Abstract: A memory addressing device for a memory divided in a plurality of elements each storing a plurality of information words. Each address for the memory comprises a first part which controls addressing means which address all the words of the memory elements stored in the address identified by said first part. All the addressed words are stored in corresponding output registers of the memory elements. The second part of the address enables the selection of the output register associated therewith. Consequently the reading operation for a block of information requires only one memory access time plus the read time of the output registers.
    Type: Grant
    Filed: August 26, 1976
    Date of Patent: May 22, 1979
    Assignee: Ing. C. Olivetti & C., S.p.A.
    Inventor: Lucio Lanza
  • Patent number: 4032895
    Abstract: An electronic computer comprising a first memory for recording instructions and data to be processed, a second memory for recording microinstructions and addressable by the instructions to provide a succession of microinstructions which is associated with each of the instructions and a third memory for recording a plurality of words and addressable by the microinstructions to provide at least one word associated with each of the microinstructions. Operation control means and a plurality of registers connectable to the control means and to the memories are provided for processing the data and two groups of signals are included in the words for controlling the operations of the control means and the registers. The control means and the registers are directly supplied with the signals of the first group for selecting the operations to be performed according to the signals of the first group.
    Type: Grant
    Filed: August 14, 1975
    Date of Patent: June 28, 1977
    Assignee: Ing. C. Olivetti & C., S.p.A.
    Inventors: Lucio Lanza, Francesco Giovanni Vecchio