Abstract: A microfluidic device is provided. In one aspect, the microfluidic device includes a microfluidic channel, and a first actuator including an array of electrodes along the microfluidic channel. The first actuator is configured to generate a a potential wave along the microfluidic channel. Each electrode of the array can see its voltage changing cyclically according to a period multiplied by a natural number, wherein for at least one electrode the natural number equals 1. The cyclically changing voltages of adjacent electrodes can be out of phase. The cyclically changing voltages of every other electrode along the array can be in phase.

Abstract: The disclosed technology generally relates to integrated circuit (IC) devices and more particularly to IC devices based on metal ion migration, and to manufacturing of the IC devices. In one aspect, a method of manufacturing an integrated electronic circuit, which includes at least one component based on metal ion migration and reduction, allows improved control of an amount of the metal which is incorporated into the component. This amount is produced from a metal supply layer and transferred into a container selectively with respect to the rest of the component. The container is configured as part of an electrolyte portion or active electrode in the final component. The method is compatible with two-dimensional and three-dimensional configurations of the component.

Abstract: The disclosed technology relates to a structure for use in a metal-insulator-metal capacitor. In one aspect, the structure comprises a bottom electrode formed of a Ru layer. The Ru layer has a top surface characterized by a grazing incidence X-ray diffraction spectrum comprising a first intensity and a second intensity, the first intensity corresponding to a diffracting plane of Miller indices (0 0 2) being larger than the second intensity corresponding to a diffracting plane of Miller indices (1 0 1). The structure further comprises an interlayer on the top surface of the Ru layer, the interlayer being formed of an oxide of Sr and Ru having a cubic lattice structure, and a dielectric layer on the interlayer, the dielectric layer being formed of an oxide of Sr and Ti.

Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

Abstract: The disclosed technology relates to a structure for use in a metal-insulator-metal capacitor. In one aspect, the structure comprises a bottom electrode formed of a Ru layer. The Ru layer has a top surface characterized by a grazing incidence X-ray diffraction spectrum comprising a first intensity and a second intensity, the first intensity corresponding to a diffracting plane of Miller indices (0 0 2) being larger than the second intensity corresponding to a diffracting plane of Miller indices (1 0 1). The structure further comprises an interlayer on the top surface of the Ru layer, the interlayer being formed of an oxide of Sr and Ru having a cubic lattice structure, and a dielectric layer on the interlayer, the dielectric layer being formed of an oxide of Sr and Ti.

Abstract: The disclosed technology generally relates to integrated circuit (IC) devices and more particularly to IC devices based on metal ion migration, and to manufacturing of the IC devices. In one aspect, a method of manufacturing an integrated electronic circuit, which includes at least one component based on metal ion migration and reduction, allows improved control of an amount of the metal which is incorporated into the component. This amount is produced from a metal supply layer and transferred into a container selectively with respect to the rest of the component. The container is configured as part of an electrolyte portion or active electrode in the final component. The method is compatible with two-dimensional and three-dimensional configurations of the component.

Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

Abstract: A Resistive Random Access Memory (RRAM) device and a method of its manufacture are disclosed. The RRAM device comprises a lower oxygen affinity bottom electrode, a hygroscopic solid-state dielectric layer, comprising hydroxyl groups, and a higher oxygen affinity top electrode. In some embodiments, the hygroscopic solid-state dielectric layer is a rare-earth metal oxide layer.

Abstract: A Conductive Bridge Random Access Memory (CBRAM) device comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the conductivity ? of the cation provided by the cation supply electrode in the electrolyte element increases towards the bottom electrode.

Abstract: A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (tf) of 100 ns or less and a pulse amplitude (If) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (ts) of 100 ns or less and a pulse amplitude (Is) equal to or larger than the forming current pulse amplitude (If).

Abstract: A Conductive Bridge Random Access Memory (CBRAM) device is disclosed, comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the cation supply electrode consists of a CuxZyeTez alloy with Z being Ge or Si and with y>15 at. %.

Abstract: A Conductive Bridge Random Access Memory (CBRAM) device comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the conductivity ? of the cation provided by the cation supply electrode in the electrolyte element increases towards the bottom electrode.

Abstract: A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (tf) of 100 ns or less and a pulse amplitude (If) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (ts) of 100 ns or less and a pulse amplitude (Is) equal to or larger than the forming current pulse amplitude (If).

Abstract: A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator.

Abstract: Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane.

Abstract: A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage application unit is arranged to write data by switching each cell between a first resistance state and a second, lower, resistance state. The voltage application unit is arranged to switch a cell to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by 0.5 volts or less. The voltage application unit is arranged to switch a cell to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by 0.5 volts or less.

Abstract: A resistive switching non-volatile memory element is disclosed comprising a resistive switching metal-oxide layer sandwiched between and in contact with a top electrode and a bottom electrode, the resistive switching metal oxide layer having a substantial isotropic non-stoichiometric metal-to-oxygen ratio. For example, the memory element may comprise a nickel oxide resistive switching layer sandwiched between and in contact with a nickel top electrode and a nickel bottom electrode whereby the ratio oxygen-to-nickel of the nickel oxide layer is between 0 and 0.85.

Abstract: Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane.