Patents by Inventor Ludwig Heitzer
Ludwig Heitzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030200Abstract: In an embodiment, a semiconductor package includes a lower surface having a low voltage contact pad, a high voltage contact pad, an output contact pad, and at least one control contact pad. The semiconductor package further includes a half-bridge circuit including a first transistor device having a first major surface and a second transistor device having a first major surface, the first and second transistor devices being electrically coupled in series at an output node, and a control device that is electrically coupled to the first transistor device and the second transistor device. The first major surface of the first transistor device and of the second transistor device are arranged substantially perpendicularly to the lower surface of the semiconductor package.Type: ApplicationFiled: July 13, 2023Publication date: January 25, 2024Inventors: Christian Irrgang, Thomas Behrens, Ludwig Heitzer, Josef Hoglauer, Thorsten Meyer, Thorsten Scharf, Frank Zudock
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Publication number: 20230369177Abstract: A molded semiconductor package includes: a mold compound; a metal substrate partly embedded in the mold compound; at least one first metal lead partly embedded in the mold compound; an inlay embedded in the mold compound, the inlay comprising a semiconductor die embedded in an electrically insulating body, a first metal structure attached to a first side of the semiconductor die, and a second metal structure attached to a second side of the semiconductor die; and a metal clip at least partly embedded in the mold compound and connecting the second metal structure to the at least one first metal lead. The semiconductor die has a maximum junction temperature higher than a glass transition temperature of the mold compound, the electrically insulating body has a glass transition temperature at or above the maximum junction temperature of the semiconductor die, and the metal substrate is attached to the first metal structure.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Inventors: Marcus Boehm, Michael Fuegl, Ludwig Heitzer, Stefan Woetzel
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Publication number: 20230341311Abstract: The application relates to a semiconductor device for particle measurement having a cavity housing and a MEMS chip arranged inside the cavity housing. The housing includes a first opening, via which the cavity is connected to the surroundings and in which a first grating is arranged, which is capable by setting it to a first electrical potential of attracting particles from the surroundings and/or electrically charging them. The MEMS chip includes a membrane facing toward the first opening, which is capable by setting it to a second electrical potential of attracting particles. The application furthermore relates to a method for operating a semiconductor device having a cavity housing and a MEMS chip arranged inside the cavity housing.Type: ApplicationFiled: April 17, 2023Publication date: October 26, 2023Inventors: Klaus ELIAN, Ludwig HEITZER, Fabian MERBELER, Matthias EBERL, Thomas MÜLLER, Andreas ALLMEIER, Derek DEBIE, Cyrus GHAHREMANI, Jens POHL, Christian IRRGANG
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Publication number: 20230194478Abstract: A radiation source device includes at least one membrane layer, a radiation source structure to emit electromagnetic or infrared radiation, a substrate and a spacer structure, wherein the substrate and the at least one membrane form a chamber, wherein a pressure in the chamber is lower than or equal to a pressure outside of the chamber, and wherein the radiation source structure is arranged between the at least one membrane layer and the substrate.Type: ApplicationFiled: October 27, 2022Publication date: June 22, 2023Inventors: Derek Debie, Klaus Elian, Ludwig Heitzer, David Tumpold, Jens Pohl, Cyrus Ghahremani, Thorsten Meyer, Christian Geissler, Andreas Allmeier
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Patent number: 10571682Abstract: A microelectromechanical systems (MEMS) package assembly and a method of manufacturing the same is provided. The MEMS package assembly includes a substrate, a housing coupled to the substrate to form a cavity, wherein the housing includes a transparent plate disposed above and parallel to the substrate and is configured to permit a transmission of light therethrough, and a MEMS chip disposed within the cavity and including a first main surface proximal to the transparent plate and a second main surface opposite to the first main surface and coupled to the substrate. The MEMS chip is oriented such that the first main surface is tilted at a tilt angle with respect to the transparent plate.Type: GrantFiled: August 10, 2017Date of Patent: February 25, 2020Assignee: Infineon Technologies AGInventors: Ludwig Heitzer, Derek Debie, Klaus Elian, Cyrus Ghahremani, Johannes Lodermeyer, Oskar Neuhoff, Johann Strasser
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Patent number: 10539779Abstract: A microelectromechanical systems (MEMS) package assembly and a method of manufacturing the same is provided. The MEMS package assembly includes a substrate, a housing coupled to the substrate to form a cavity, wherein the housing includes a transparent plate disposed above and parallel to the substrate and is configured to permit a transmission of light therethrough, and a MEMS chip disposed within the cavity and including a first main surface proximal to the transparent plate and a second main surface opposite to the first main surface and coupled to the substrate. The MEMS chip is oriented such that the first main surface is tilted at a tilt angle with respect to the transparent plate.Type: GrantFiled: August 10, 2017Date of Patent: January 21, 2020Assignee: Infineon Technologies AGInventors: Ludwig Heitzer, Derek Debie, Klaus Elian, Cyrus Ghahremani, Johannes Lodermeyer, Oskar Neuhoff, Johann Strasser
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Patent number: 10424819Abstract: A semiconductor battery includes a substrate, a battery anode semiconductor material arranged in or over the substrate, a battery cathode material arranged in or over the substrate and a battery electrolyte disposed between the battery anode semiconductor material and the battery cathode material. An electrically insulating encapsulant has a first face and a second face. The substrate is at least partly embedded in the encapsulant. An anode electrode is electrically connected to the battery anode semiconductor material and is disposed over the second face of the encapsulant. A cathode electrode is electrically connected to the battery cathode material and is disposed over the first face of the encapsulant.Type: GrantFiled: March 20, 2017Date of Patent: September 24, 2019Assignee: Infineon Technologies Dresden GmbH & Co. KGInventors: Hans Ehm, Ludwig Heitzer, Marko Lemke, Claudius Von Petersdorff-Campen
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Publication number: 20190049716Abstract: A microelectromechanical systems (MEMS) package assembly and a method of manufacturing the same is provided. The MEMS package assembly includes a substrate, a housing coupled to the substrate to form a cavity, wherein the housing includes a transparent plate disposed above and parallel to the substrate and is configured to permit a transmission of light therethrough, and a MEMS chip disposed within the cavity and including a first main surface proximal to the transparent plate and a second main surface opposite to the first main surface and coupled to the substrate. The MEMS chip is oriented such that the first main surface is tilted at a tilt angle with respect to the transparent plate.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Applicant: Infineon Technologies AGInventors: Ludwig HEITZER, Derek DEBIE, Klaus ELIAN, Cyrus GHAHREMANI, Johannes LODERMEYER, Oskar NEUHOFF, Johann STRASSER
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Patent number: 10043768Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line.Type: GrantFiled: May 12, 2015Date of Patent: August 7, 2018Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Ludwig Heitzer
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Patent number: 9881909Abstract: A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first semiconductor die and a first solder interconnect layer applied to a main face of the first semiconductor die. The second semiconductor chip has a second semiconductor die, an insulating layer applied to a main face of the second semiconductor die, and a second solder interconnect layer applied to the insulating layer. The method further includes attaching the first semiconductor chip with the first solder interconnect layer to a first carrier and attaching the second semiconductor chip with the second solder interconnect layer to a second carrier.Type: GrantFiled: October 29, 2015Date of Patent: January 30, 2018Assignee: Infineon Technologies AGInventors: Michael Bauer, Ludwig Heitzer, Christian Stuempfl
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Publication number: 20170271722Abstract: A semiconductor battery includes a substrate, a battery anode semiconductor material arranged in or over the substrate, a battery cathode material arranged in or over the substrate and a battery electrolyte disposed between the battery anode semiconductor material and the battery cathode material. An electrically insulating encapsulant has a first face and a second face. The substrate is at least partly embedded in the encapsulant. An anode electrode is electrically connected to the battery anode semiconductor material and is disposed over the second face of the encapsulant. A cathode electrode is electrically connected to the battery cathode material and is disposed over the first face of the encapsulant.Type: ApplicationFiled: March 20, 2017Publication date: September 21, 2017Inventors: Hans Ehm, Ludwig Heitzer, Marko Lemke, Claudius Von Petersdorff-Campen
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Patent number: 9576935Abstract: A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body.Type: GrantFiled: April 16, 2014Date of Patent: February 21, 2017Assignee: Infineon Technologies AGInventors: Michael Bauer, Ludwig Heitzer, Christian Stuempfl
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Publication number: 20160379945Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line.Type: ApplicationFiled: May 12, 2015Publication date: December 29, 2016Inventors: Thorston MEYER, Ludwig HEITZER
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Publication number: 20160126227Abstract: A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first semiconductor die and a first solder interconnect layer applied to a main face of the first semiconductor die. The second semiconductor chip has a second semiconductor die, an insulating layer applied to a main face of the second semiconductor die, and a second solder interconnect layer applied to the insulating layer. The method further includes attaching the first semiconductor chip with the first solder interconnect layer to a first carrier and attaching the second semiconductor chip with the second solder interconnect layer to a second carrier.Type: ApplicationFiled: October 29, 2015Publication date: May 5, 2016Inventors: Michael Bauer, Ludwig Heitzer, Christian Stuempfl
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Publication number: 20150303135Abstract: A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body.Type: ApplicationFiled: April 16, 2014Publication date: October 22, 2015Applicant: Infineon Technologies AGInventors: Michael Bauer, Ludwig Heitzer, Christian Stuempfl
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Patent number: 9030019Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.Type: GrantFiled: December 14, 2010Date of Patent: May 12, 2015Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Ludwig Heitzer
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Patent number: 8421226Abstract: A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body.Type: GrantFiled: February 25, 2010Date of Patent: April 16, 2013Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Ludwig Heitzer, Dominic Maier
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Patent number: 8330260Abstract: A method for producing an electronic component of a VQFN (very thin quad flat pack no-lead) design includes the following method steps: anchoring at least one integrated circuit element on a sacrificial substrate; contact-connecting the at least one integrated circuit element to the sacrificial substrate with formation of contact-connecting points on the sacrificial substrate; forming an encapsulation on a top side of the sacrificial substrate, the at least one anchored integrated circuit element being mounted on the top side of the sacrificial substrate; removing the sacrificial substrate, thereby uncovering a portion of the contact-connecting points on the underside of the encapsulation.Type: GrantFiled: July 20, 2007Date of Patent: December 11, 2012Assignee: Infineon Technologies AGInventors: Michael Bauer, Ludwig Heitzer, Christian Stuempfl
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Publication number: 20120146231Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Inventors: Thorsten Meyer, Ludwig Heitzer
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Patent number: 8173488Abstract: This application relates to a method of manufacturing a semiconductor device comprising: providing multiple chips each comprising contact elements on a first main face of each of the multiple chips, and a first layer applied to each of the first main faces of the multiple chips; placing the multiple chips over a carrier with the first layers facing the carrier; applying encapsulation material to the multiple chips and the carrier to form an encapsulation workpiece embedding the multiple chips; and removing the carrier from the encapsulation workpiece.Type: GrantFiled: September 30, 2008Date of Patent: May 8, 2012Assignee: Intel Mobile Communications GmbHInventors: Michael Bauer, Ludwig Heitzer, Daniel Porwol