Abstract: A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body.

Abstract: A plastic housing includes plastic external faces and the underside of the plastic housing comprises external contact areas on which external contacts are arranged. The plastic external faces are covered by a closed metal layer apart from the underside, wherein the boundary layer between plastic external faces and the closed metal layer includes exposed electrically conductive inclusions of the plastic of the housing.

Abstract: The invention pertains to a method for manufacturing an electronic component with a semiconductor element (1) that is contacted and fixed on a substrate surface (2). The method is characterized in that the rear side of the semiconductor element and/or the substrate surface is coated with an adhesive structure consisting of a first component (3) that solidifies, particularly hardens or cures, and an electrically conductive second component (4) that does not solidify, wherein the semiconductor element is bonded to the substrate surface in a contacting fashion. The electronic component is characterized in that a structured adhesive layer arranged between the semiconductor element and the substrate surface comprises a solidifying first component (3) and an electrically conductive non-solidifying second component (4).

Abstract: A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected to a chip pad of a circuit carrier via an electrically conductive layer. In another embodiment, the thinned semiconductor chips of this semiconductor device according to the invention have low-microdefect edge side regions with semiconductor element structures and edge sides patterned by etching technology.

Abstract: An electronic circuit in a package-in-package configuration and a production method is disclosed. One embodiment provides an arrangement enveloped by an encapsulation and composed of at least one semiconductor element on an element carrier, at least one leadframe with at least one inner contact-connection, at least one inner lead running within the encapsulation, and at least one outer contact-connection led out from the encapsulation. The inner lead has an exposed inner lead section which can be contact-connected from the outer side of the package-in-package configuration.

Abstract: This application relates to a method of manufacturing a semiconductor device comprising: providing multiple chips each comprising contact elements on a first main face of each of the multiple chips, and a first layer applied to each of the first main faces of the multiple chips; placing the multiple chips over a carrier with the first layers facing the carrier; applying encapsulation material to the multiple chips and the carrier to form an encapsulation workpiece embedding the multiple chips; and removing the carrier from the encapsulation workpiece.

Abstract: A module (100) comprises a component (10) and a shielding element (11), which is mounted on a main surface (12) of the component (10) and has a welding contact (13).

Abstract: An electronic circuit in a package-on-package configuration includes: a lower subassembly with a first electronic element, a first wiring carrier, a first housing with a first redistribution layer and an arrangement of solder balls disposed on the first redistribution layer and an upper subassembly with a second electronic element mounted on the lower subassembly. A method for producing the electronic circuit in a package-on-package configuration includes: adhering an upper side of the first electronic element to an underside of the first redistribution layer via a radiation-crosslinking thermoplastic adhesive.

Abstract: A structure of joining material is applied to the back surfaces of semiconductor chips in manufacturing semiconductor devices. The joining material is applied, in finely metered and structured form via a joining material jet appliance, to the back surfaces of the semiconductor chips of a divided semiconductor wafer.

Abstract: A method for coating a structure that includes at least one semiconductor chip involves electrostatically depositing coating particles on the areas of the structure to be coated. The coating particles are first applied to a carrier and the latter is electrostatically charged with the coating particles. The structure including at least one semiconductor chip is charged electrostatically to a polarity opposite to the carrier. The carrier and/or the structure are then moved towards one another in the direction of an area of the structure to be coated until the coating particles jump to the areas of the structure to be coated and adhere there. The coating particles are liquefied by heating the area with coating particles to form a coating.

Abstract: A semiconductor device includes a semiconductor chip and an adhesive film between the back side of the semiconductor chip and a chip pad of a leadframe. The adhesive film includes a film core and adhesive layers that cover both sides of the film core. The film core includes a brittle, fragile hard material.

Abstract: A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected to a chip pad of a circuit carrier via an electrically conductive layer. In another embodiment, the thinned semiconductor chips of this semiconductor device according to the invention have low-microdefect edge side regions with semiconductor element structures and edge sides patterned by etching technology.

Abstract: A chip (1) or a semiconductor wafer having a contact element (2) for electrical contact-connection is described. In this case, the contact element (2) is covered with an organic layer (3).

Abstract: A module (100) comprises a component (10) and a shielding element (11), which is mounted on a main surface (12) of the component (10) and has a welding contact (13).

Abstract: Chip arrangement and method for producing a chip arrangement A chip arrangement comprises a first chip with an electrically operable structure on an active surface of the first chip. The first chip is applied on a carrier area in order to make electrical contact with the electrically operable structure via the carrier area. A second chip has a cutout and is arranged on the carrier area, the first chip being arranged in a cavity formed by the cutout and the carrier area.

Abstract: A plastic housing includes plastic external faces and the underside of the plastic housing comprises external contact areas on which external contacts are arranged. The plastic external faces are covered by a closed metal layer apart from the underside, wherein the boundary layer between plastic external faces and the closed metal layer includes exposed electrically conductive inclusions of the plastic of the housing.

Abstract: An electronic device is produced by providing a carrier wafer formed from at least a semiconductor material, apply a wiring structure with conductor tracks and contact pads to a top side of the carrier wafer so as to form a plurality of semiconductor device positions arranged in rows and columns along the carrier wafer. Integrated circuit chips are applied in the semiconductor device positions and embedded into a plastic housing composition, thereby forming a composite plate including the integrated circuit chips and the plastic housing composition. After curing the plastic housing composition, the carrier wafer is removed.

Abstract: A method for producing an electronic component of a VQFN (very thin quad flat pack no-lead) design includes the following method steps: anchoring at least one integrated circuit element on a sacrificial substrate; contact-connecting the at least one integrated circuit element to the sacrificial substrate with formation of contact-connecting points on the sacrificial substrate; forming an encapsulation on a top side of the sacrificial substrate, the at least one anchored integrated circuit element being mounted on the top side of the sacrificial substrate; removing the sacrificial substrate, thereby uncovering a portion of the contact-connecting points on the underside of the encapsulation.

Abstract: An electronic circuit in a package-in-package configuration and a production method is disclosed. One embodiment provides an arrangement enveloped by an encapsulation and composed of at least one semiconductor element on an element carrier, at least one leadframe with at least one inner contact-connection, at least one inner lead running within the encapsulation, and at least one outer contact-connection led out from the encapsulation. The inner lead has an exposed inner lead section which can be contact-connected from the outer side of the package-in-package configuration.

Abstract: An electronic circuit in a package-on-package configuration includes: a lower subassembly with a first electronic element, a first wiring carrier, a first housing with a first redistribution layer and an arrangement of solder balls disposed on the first redistribution layer and an upper subassembly with a second electronic element mounted on the lower subassembly. A method for producing the electronic circuit in a package-on-package configuration includes: adhering an upper side of the first electronic element to an underside of the first redistribution layer via a radiation-crosslinking thermoplastic adhesive.