Abstract: A magnetoresistive effect memory (100) includes: a magnetoresistive element (11) including a fixed layer (111) whose magnetization direction is fixed and a recording layer (113) whose magnetization direction changes; and a write circuit (24) that reverses magnetization of the recording layer (113) so that a resistance value of the magnetoresistive element (11) is switched between a low resistance value and a high resistance value, in which the magnetization of the recording layer (113) rotates by precession around a magnetic field in a plane direction of the layer when a voltage is applied to the magnetoresistive element (11), the resistance value of the magnetoresistive element (11) gradually changes between the low resistance value and the high resistance value during the rotation of the magnetization of the recording layer (113), and the write circuit (24) reverses the magnetization of the recording layer (113) so that the resistance value of the magnetoresistive element (11) is switched from the high resi

Abstract: A second magnetic layer (13) of a magnetoresistive element (100) is a perpendicular magnetization layer when no voltage (V) is applied to the magnetoresistive element (100), changes from the perpendicular magnetization layer to an in-plane magnetization layer when a first voltage (V1) is applied to the magnetoresistive element (100), and changes from the perpendicular magnetization layer to the in-plane magnetization layer when a second voltage (V2) is applied to the magnetoresistive element (100). Magnetization of the second magnetic layer (13) changes to a first direction of a direction perpendicular to a plane of the layer after a third voltage (V3) is applied to the magnetoresistive element (100) for a first period of time and changes to a second direction of the direction perpendicular to the plane of the layer after a fourth voltage (V4) is applied to the magnetoresistive element (100) for a second period of time.

Abstract: A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n?1-bit write data excluding data of a least significant bit among n-bit write data into n?1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.

Abstract: A configuration of an electronic device is to be simplified. The electronic device includes a magnetoresistive effect memory, a memory control unit, and a processing unit. The magnetoresistive effect memory holds first data to be written with verification and second data to be written without verification. The memory control unit writes the first data and the second data into the magnetoresistive effect memory and verifies the first data. The processing unit performs processing based on the first data and the second data.

Abstract: A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.

Abstract: To achieve simplification of writing to magnetoresistive effect memory. The magnetoresistive effect memory includes a magnetoresistive effect element (120). The magnetoresistive effect element (120) provided in the magnetoresistive effect memory includes: a voltage-controlled magnetic anisotropy effect layer (first magnetization free layer 141) that is a magnetization free layer having a variable magnetization direction and has a voltage-controlled magnetic anisotropy effect; a non-voltage-controlled magnetic anisotropy effect layer (second magnetization free layer 143) that is a magnetization free layer having a variable magnetization direction and has no voltage-controlled magnetic anisotropy effect; and a magnetization fixed layer (122) that has a magnetic anisotropy and has an invariable magnetization direction.

Abstract: To reduce a time period required for writing data.

Abstract: A magnetoresistive element according to the present embodiment includes a first magnetic layer (11) stacked on a base layer (10), a second magnetic layer (13), and a first nonmagnetic layer (12) arranged between the first magnetic layer (11) and the second magnetic layer (13). The first nonmagnetic layer (12) includes an insulating material including fluorine.

Abstract: A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.

Abstract: A controller includes a processing circuit that writes each of a plurality of data fragments each including a part of data to be written in one memory chip of a plurality of memory chips each having an error correction function, and reads the data fragments corresponding to the data to be read from the memory chips, a first encoder that encodes the data to be written with an erasure correction code such that each of the data fragments includes a parity, and a first decoder that performs erasure correction by use of a part of the data fragments corresponding to the data to be read according to a completion status or success or failure of error correction on a corresponding part of the data fragments in each of the memory chips, the completion status or the success or failure of the error correction being acquired via a signal line.

Abstract: A memory cell array unit according to an embodiment of the present disclosure includes a memory cell array and a microcontroller. The memory cell array includes an n-bit allocation bit allocated from a memory controller in read/write control, and a redundant bit of one or a plurality of bits not being provided with a switching mechanism that switches as a substitution for a portion of the allocation bit. The microcontroller reads and writes n-bit data from and into the memory cell array using the allocation bit and the redundant bit on the basis of the read/write control from the memory controller.

Abstract: A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n?1-bit write data excluding data of a least significant bit among n-bit write data into n?1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.

Abstract: Provided are a controller and a storage device that achieve both high reliability and performance. A controller according to the present disclosure includes: a processing circuit configured to write each of a plurality of data fragments each including a part of data to be written in one memory chip of a plurality of memory chips each having an error correction function, and read the data fragments corresponding to the data to be read from the memory chips; a first encoder configured to encode the data to be written with an erasure correction code such that each of the data fragments includes a parity; and a first decoder configured to perform erasure correction by use of a part of the data fragments corresponding to the data to be read according to a completion status or success or failure of error correction on a corresponding part of the data fragments in each of the memory chips, the completion status or the success or failure of the error correction being acquired via a signal line.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method that make it possible to more reliably transmit a transmission control signal. Provided is a transmission device including a transmission unit that includes a first transmission control signal compatible with a first system in a first broadcast signal including a signal of a first content compatible with the first system and a signal of a second content compatible with a second system and transmits the first broadcast signal via a first transmission antenna, and includes a second transmission control signal compatible with the second system in a second broadcast signal including the signal of the second content and transmits the second broadcast signal via a second transmission antenna. The present technology can be applied to, for example, a transmission system compatible with a broadcast system such as an ISDB-T system.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method that make it possible to more reliably transmit a transmission control signal. Provided is a transmission device including a transmission unit that includes a first transmission control signal compatible with a first system in a first broadcast signal including a signal of a first content compatible with the first system and a signal of a second content compatible with a second system and transmits the first broadcast signal via a first transmission antenna, and includes a second transmission control signal compatible with the second system in a second broadcast signal including the signal of the second content and transmits the second broadcast signal via a second transmission antenna. The present technology can be applied to, for example, a transmission system compatible with a broadcast system such as an ISDB-T system.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method that make it possible to improve transmission efficiency. Provided is a transmission device including a first time interleaver that performs first time interleaving conforming to a first system, on an error correction code block to be included as a data frame in a physical layer frame, in which the error correction code block conforms to a second system, and when performing the first time interleaving, the first time interleaver applies a pointer indicating an offset of a start position of the error correction code block included at a start of the data frame. The present technology can be applied to, for example, a transmission system compatible with a broadcast system such as an ISDB-T system.

Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.

Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Abstract: To enable data to be transferred between a memory and a memory controller with accuracy. A memory-side interface circuit synchronizes a first periodic signal having a greater number of cycles than a number of pieces of unit data obtained by dividing read data read from a memory cell by a predetermined unit with the unit data and to sequentially transmit the first periodic signal and the unit data. A controller-side interface circuit sequentially holds the transmitted unit data in holding units of a plurality of stages in synchronization with the periodic signal and sequentially reads and outputs the held unit data in synchronization with a second periodic signal.

Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.