Abstract: An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.

Abstract: A controller includes: a low-level error correction section configured to execute low-level error correction in which an error in a code word is corrected with use of a predetermined decoding algorithm; and a high-level soft-decision error correction section configured to execute high-level soft-decision error correction in which the error in the code word is corrected with use of a high-level algorithm when the error correction by the low-level error correction section has failed, the high-level algorithm being a soft-decision decoding algorithm having higher error correction capability than error correction capability of the predetermined decoding algorithm.

Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Abstract: An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected.

Abstract: A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus.

Abstract: Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a first operation from among the first operation and a second operation, in a memory cell array in which each bit transitions to a first storage state by the first operation and transitions to a second storage state by the second operation; and a request unit which makes a request for the first rewriting process with respect to the memory cell array, when the first timing is detected.

Abstract: The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4.

Abstract: An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails.

Abstract: The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc?Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword por

Abstract: An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.

Abstract: A controller includes: a low-level error correction section configured to execute low-level error correction in which an error in a code word is corrected with use of a predetermined decoding algorithm; and a high-level soft-decision error correction section configured to execute high-level soft-decision error correction in which the error in the code word is corrected with use of a high-level algorithm when the error correction by the low-level error correction section has failed, the high-level algorithm being a soft-decision decoding algorithm having higher error correction capability than error correction capability of the predetermined decoding algorithm.

Abstract: An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected.

Abstract: Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Abstract: The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.

Abstract: The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors. Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.

Abstract: The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4.

Abstract: Disclosed herein is a receiving apparatus including a reception device configured to receive a code sequence coded in LDPC (Low Density Parity Check) and punctured at least partially as a target to be decoded; and an LDPC decoding device configured to perform a punctured matrix transform process including a first and a second process on an original parity check matrix noted to have punctured bits or symbols and used in the LDPC coding. The LDPC decoding device further performs the first process to carry out Galois field addition operations on those rows of the original parity check matrix to set the non-zero elements to zero. The LDPC decoding device further performs the second process to delete the columns rid of the non-zero elements. The LDPC decoding device uses the matrix resulting from the process as the parity check matrix for performing an LDPC decoding process on the code sequence.

Abstract: The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc?Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword por

Abstract: Disclosed herein is a receiving apparatus including a reception device configured to receive a code sequence coded in LDPC (Low Density Parity Check) and punctured at least partially as a target to be decoded; and an LDPC decoding device configured to perform a punctured matrix transform process including a first and a second process on an original parity check matrix noted to have punctured bits or symbols and used in the LDPC coding. The LDPC decoding device further performs the first process to carry out Galois field addition operations on those rows of the original parity check matrix to set the non-zero elements to zero. The LDPC decoding device further performs the second process to delete the columns rid of the non-zero elements. The LDPC decoding device uses the matrix resulting from the process as the parity check matrix for performing an LDPC decoding process on the code sequence.

Abstract: The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors. Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.