Abstract: According to an aspect, summarizing relevance of a document to a conceptual query includes receiving the conceptual query, accessing concepts extracted from the document, and computing a degree to which the conceptual query is related to each of the extracted concepts. The computing is responsive to a metric that measures a relevance between the concepts in the conceptual query and the extracted concepts. An aspect also includes creating a summary by selecting a threshold number of the concepts having a greatest degree of relation to the conceptual query, and outputting the summary including the selected threshold number of concepts.

Abstract: According to an aspect, conceptual analysis of a document includes accessing a concept graph that includes a plurality of nodes and edges. Each node represents a concept and each edge represents a known relation between two concepts. Conceptual analysis of the document further includes computing a relevance of the document to concepts in the concept graph. The computing includes receiving a priori information about the document including concepts extracted from the document. The concepts extracted from the document include a subset of the concepts in the concept graph. The computing also includes combining the a priori information and the concept graph to generate a posteriori information that indicates a likelihood that the document is related to each of the concepts in the concept graph.

Abstract: A hybrid encryption scheme for storing data lines in a memory includes identifying data lines determined to be frequently accessed, and encrypting the data lines using a first encryption scheme. The hybrid encryption scheme also includes encrypting data lines determined not to be frequently accessed using a second encryption scheme.

Abstract: Embodiments of the invention relates to avoiding out-of-space conditions in storage controllers operating with efficiency capabilities between virtual space in a data container and real space in a storage container. Both the real space and the virtual space are monitored and their respective usage is compared to provide information about occupancy of the real space to the virtual space. Usage of the containers is balanced by employing a virtual file associated with a reserved portion of free capacity in the virtual space.

Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.

Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.

Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) memory module communications with a host processor in multi-ported memory configurations in a computer system. Each of multiple memory modules operating in unison is enabled to identify which memory module is the one required to communicate module specific information back to the host processor. All of the multiple memory modules operating in unison are enabled to generate back to the host processor a valid ECC word, while other multiple memory modules individually being unaware of data contents of the one memory module required to communicate back to the processor.

Abstract: A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.

Abstract: A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software.

Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

Abstract: A hybrid encryption scheme for storing data lines in a memory includes identifying data lines determined to be frequently accessed, and encrypting the data lines using a first encryption scheme. The hybrid encryption scheme also includes encrypting data lines determined not to be frequently accessed using a second encryption scheme.

Abstract: Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.

Abstract: Errors on a dynamic random access memory (“DRAM”) having an error correcting decoder (“ECC”) can be detected by the ECC when reading a row of the DRAM. The ECC includes error correcting code logic. If errors are detected that cannot be corrected by the ECC logic, test control logic determines weak cell information for the row, evaluates the errors using the weak cell information, and may correct the errors. The weak cell information may include weak cell locations and failure values.

Abstract: Correction of structured burst errors in data is provided by a system that includes an encoder and is configured for performing a method. The method includes receiving data that includes a plurality of subsets of data. The data is encoded by an encoder using a combination of a first error correcting code and a second error correcting code. The first error correcting code is configured to provide error recovery from a structured burst error in one of the subsets of data, the structured burst error having a length less than a specified maximum length. The second error correcting code is configured to extend the first error correcting code to provide error recovery from the structured burst error in any of the subsets of data. The encoded data is output.

Abstract: Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.

Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.

Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.