Patents by Inventor Luis-Felipe Giles

Luis-Felipe Giles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230068318
    Abstract: Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×1017 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 1017 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Intel Corporation
    Inventors: Richard Geiger, Georgios Panagopoulos, Luis Felipe Giles, Peter Baumgartner, Harald Gossner, Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then
  • Patent number: 9159830
    Abstract: In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 13, 2015
    Assignee: Infineon Technologies AG
    Inventors: Luis-Felipe Giles, Frank Lau, Rainer Liebmann
  • Publication number: 20140252498
    Abstract: In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: Infineon Technologies AG
    Inventors: Luis-Felipe Giles, Frank Lau, Rainer Libermann
  • Patent number: 8772097
    Abstract: In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Luis-Felipe Giles, Frank Lau, Rainer Liebmann
  • Patent number: 8357995
    Abstract: A semiconductor element including a substrate and at least one shallow junction formed in the substrate wherein doping atoms are disposed in the shallow junction. A plurality of carbide precipitates and micro-cavities is disposed in the substrate below the at least one shallow junction.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: January 22, 2013
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7977167
    Abstract: A method of producing a field effect transistor arrangement. A substrate having a first crystal surface orientation is provided. A first layer is formed above a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation. A second layer is formed on at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation. A first buried oxide layer is formed between the substrate and the first layer. Micro-cavities are formed in the second layer and oxidizing the micro-cavities, thereby forming a second buried oxide layer between the substrate and the second layer. A first field effect transistor of a first conductivity type is formed in or on the first layer. A second field effect transistor of a second conductivity type is formed in or on the second layer.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Infineon Technologies AG
    Inventors: Karl Hofmann, Luis-Felipe Giles
  • Patent number: 7972947
    Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 5, 2011
    Assignees: Infineon Technologies AG, IMEC VZW.
    Inventors: Luis-Felipe Giles, Thomas Hoffmann, Chris Stapelmann
  • Patent number: 7887634
    Abstract: In a method of producing a semiconductor element in a substrate, a plurality of carbide precipitates is formed in the substrate, doping atoms are implanted into the substrate, thereby forming crystal defects in the substrate, the substrate is heated, such that at least a part of the crystal defects is eliminated using the carbide precipitates, and the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: February 15, 2011
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7867861
    Abstract: A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: January 11, 2011
    Assignee: Infineon Technologies AG
    Inventors: Luis-Felipe Giles, Rainer Liebmann, Chris Stapelmann
  • Patent number: 7833886
    Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 16, 2010
    Assignees: Infineon Technologies AG, Qimonda AG
    Inventors: Luis-Felipe Giles, Matthias Goldbach, Martin Bartels, Paul Kuepper
  • Patent number: 7825016
    Abstract: In a method for fabricating a semiconductor element in a substrate, micro-cavities are formed in the substrate. Furthermore, doping atoms are implanted into the substrate, whereby crystal defects are produced in the substrate. The substrate is heated, so that at least some of the crystal defects are eliminated using the micro-cavities, and the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7749875
    Abstract: A method of manufacturing a semiconductor element. A dislocation region is formed between a first layer and a second layer, the dislocation region including a plurality of dislocations. First interstitials in the first layer are at least partially eliminated using the dislocations in the dislocation region. Vacancies are formed in the second layer. Second interstitials in the second layer are at least partially eliminated using the vacancies in the second layer.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: July 6, 2010
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Publication number: 20100127262
    Abstract: A semiconductor element including a substrate and at least one shallow junction formed in the substrate wherein doping atoms are disposed in the shallow junction. A plurality of carbide precipitates and micro-cavities is disposed in the substrate below the at least one shallow junction.
    Type: Application
    Filed: December 18, 2009
    Publication date: May 27, 2010
    Inventor: Luis-Felipe Giles
  • Publication number: 20100041185
    Abstract: A method of producing a field effect transistor arrangement. A substrate having a first crystal surface orientation is provided. A first layer is formed above a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation. A second layer is formed on at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation. A first buried oxide layer is formed between the substrate and the first layer. Micro-cavities are formed in the second layer and oxidizing the micro-cavities, thereby forming a second buried oxide layer between the substrate and the second layer. A first field effect transistor of a first conductivity type is formed in or on the first layer. A second field effect transistor of a second conductivity type is formed in or on the second layer.
    Type: Application
    Filed: October 23, 2009
    Publication date: February 18, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Karl HOFMANN, Luis-Felipe GILES
  • Patent number: 7662680
    Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part of the crystallographic defects are eliminated using the micro-cavities and the carbide precipitates, and wherein the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 16, 2010
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Publication number: 20090085110
    Abstract: A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the silicon of the silicon substrate at the desired target depth, and forming a source region and a drain region in the substrate such that a channel region there between is positioned above the band of precipitates, wherein the desired target depth is such that a desired separation distance is achieved between the channel region and the band of precipitates, and wherein an average lattice constant of the band of precipitates is different from the average lattice constant of the silicon substrate so as to cause a stress in the channel region.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Luis-Felipe Giles, Rainer Liebmann, Chris Stapelmann
  • Publication number: 20090085035
    Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part of the crystallographic defects are eliminated using the micro-cavities and the carbide precipitates, and wherein the semiconductor element is formed using the doping atoms.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventor: Luis-Felipe Giles
  • Publication number: 20080290425
    Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 27, 2008
    Inventors: Luis-Felipe Giles, Thomas Hoffmann, Chris Stapelmann
  • Publication number: 20080286908
    Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms.
    Type: Application
    Filed: May 14, 2007
    Publication date: November 20, 2008
    Inventors: Luis-Felipe Giles, Matthias Goldbach, Martin Bartels, Paul Kuepper
  • Publication number: 20080203484
    Abstract: A field effect transistor arrangement and a fabrication method thereof. The field effect transistor arrangement includes: a substrate having a first crystal surface orientation; a first layer formed above at least a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation; a second layer formed above at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation; a first buried oxide layer formed between the first layer and the substrate; a second buried oxide layer formed between the second layer and the substrate; a first field effect transistor formed in or on the first layer, the first field effect transistor having a first conductivity type; and a second field effect transistor formed in or on the second layer, the second field effect transistor having a second conductivity type different from the first conductivity type.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Karl Hofmann, Luis-Felipe Giles