Abstract: An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.

Abstract: An automated system for cleaning solar panels in a solar plant, characterized in that it comprises: at least one chassis, which comprises at least two vertical bars; and at least one longitudinal upper bar, which joins the at least two vertical bars; at least two wheels, arranged at one of the ends of each of the at least two vertical bars; at least one cleaning element; at least one driving means, to mobilize the at least two wheels; and at least one controller means, to control the operation of each of the at least two wheels.

Abstract: Disclosed in the present is materials and methods for delivering substances to plants. The invention describes a method to enhance substances uptake by plants using selective ablation of light pulses to remove the wax cuticle on a large scale in fields, comprising steps of light selective ablation of wax based optical properties of leaves, using lasers, pulsed lamps or other light sources like solar filtered solar light to remove the wax selectively without damage the leaves. Also disclosed is material for enhancing substances uptake by plants using selective ablation of light pulses to remove the wax cuticle, comprising selective ablation of light pulses of a wavelength of about 532 nm or within the range 495 to 570 nm.

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

Abstract: A molded part includes a plurality of surfaces and an embossment extending from one of the plurality of surfaces. The embossment includes a body and a bore extending through a central portion of the body. The embossment further includes a first pocket extending through a sidewall of the body and into the bore and a second pocket extending through an opposite sidewall of the body and into the bore. The first pocket and the second pocket each define inwardly tapered walls. The first pocket and the second pocket are spaced axially along the body and are diametrically opposed.

Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

Abstract: In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

Abstract: An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

Abstract: In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

Abstract: A modular firearm holster safety retention assembly is operable with a holster to prevent unauthorized extraction or accidental drop of a firearm from holster. The assembly comprises a saddle that receives the barrel of a firearm, and a pivot release arm that couples to the saddle to selectively restrict movement or release the firearm in the holster. The pivot release arm detachably couples to the saddle. The pivot release arm has a first end with a protruding locking nub that engages the ejection port of firearm to restrict movement thereof; and a second end that is urged away from the saddle to disengage the locking nub from the firearm ejection port to disengage firearm from saddle. The saddle and the pivot release arm have interlocking wedges that restrict forceful removal of the firearm from holster. The saddle has a pivot stop to prevent overleveraging of pivot release arm.

Abstract: A molded part includes a plurality of surfaces and an embossment extending from one of the plurality of surfaces. The embossment includes a body and a bore extending through a central portion of the body. The embossment further includes a first pocket extending through a sidewall of the body and into the bore and a second pocket extending through an opposite sidewall of the body and into the bore. The first pocket and the second pocket each define inwardly tapered walls. The first pocket and the second pocket are spaced axially along the body and are diametrically opposed.

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Abstract: A key fob includes selectors for performing conventional remote operations (e.g., locking/unlocking doors) as well as a “pet mode” selector. When the pet mode selector is pressed by a user, a coded wireless signal is sent to a vehicle computer. The vehicle computer is operatively connected to multiple vehicle systems that each controls various features of the vehicle. Responsive to receipt of the coded wireless signal, the vehicle computer instructs a selected group of the systems to operate in a specified manner so as to create a comfortable environment for a pet within the vehicle. For example, in pet mode, the vehicle computer may cause one or more windows to lower, the sunroof to open the trunk lift gate to pivot open, and the seat backs of one or more rows of seats to tilt or fold down.

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Abstract: A modular firearm holster safety retention. assembly is operable with a holster to prevent unauthorized extraction or accidental drop of a firearm from holster. The assembly comprises a saddle that receives the barrel of a firearm, and a pivot release arm that couples to the saddle to selectively restrict movement or release the firearm in the holster. The pivot release arm detachably couples to the saddle. The pivot release arm has a first end with a protruding locking nub that engages the ejection port of firearm to restrict movement thereof; and a second end that is urged away from the saddle to disengage the locking nub from the firearm ejection port to disengage firearm from saddle. The saddle and the pivot release arm have interlocking wedges that restrict forceful removal of the firearm from holster. The saddle has a pivot stop to prevent overleveraging of pivot release arm.

Abstract: A modular firearm protection and alignment assembly and method of operation integrates with a firearm holster to align and protect the firearm. The assembly is arranged, such that a firearm is centrally aligned, and provided with a fixed stopping point in the holster. An upper base includes a platform defined by a protruding alignment member that projects upwardly from the platform. The platform serves as a barrier to prevent the firearm from sliding beyond a predetermined point into the holster. The protruding alignment member projects from the bottom of the holster to receive, and concentrically align, the barrel of the firearm with the holster. A lower base joins with the upper base through use of a fastening mechanism. The lower base has an elongated panel that couples to the upper base, and a circular panel that protects light accessories mounted on the firearm, and drains fluids from the holster.

Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.