Abstract: An active filter and an analog-to-digital converter (ADC) configured to suppress out-of-band peaking. An active filter may include an active device configured to provide a power gain to an input signal, a feedback network configured to connect an output of the active device to an input of the active device, and an input impedance network configured to couple the input signal to the input of the active device. A combination of the feedback network and the input impedance network is configured to provide frequency response properties of the active filter such that a frequency domain signal transfer function of the active filter has a constant in numerator.

Abstract: Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.

Abstract: Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.

Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

Abstract: Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first “pre-modulation” tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second “modulation” phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.

Abstract: A receiver circuit for receiving an analog signal comprises a mixer device, a first integrator device coupled to the mixer device, a second integrator device following the first integrator device, a quantizer device, and first and second feedback digital/analog converters. The mixer device mixes the analog signal with a local-oscillator frequency and outputs a mixer current signal. The first integrator device generates a first intermediate signal by integrating the mixer current signal summed with a first feedback current signal, the second integrator device generates a quantizer input signal by integrating the first intermediate signal summed with a second feedback current signal, and the quantizer device generates a digital output signal by quantizing the quantizer input signal.

Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

Abstract: In a method for starting a circuit arrangement an output signal of a circuit arrangement with interlinked feedback control circuits is utilized as a control variable for the feedback control circuits and an input signal for the circuit arrangement is damped for a predetermined time period during a starting phase of the circuit arrangement.

Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

Abstract: The invention relates to a power-saving multibit delta-sigma converter (1) comprising: an input (2) for an analog input signal (ZA) and an output (3) for a digital output signal (ZD); a digital-to-analog converter (4) having a bit width N and serving to convert the digital output signal (ZD) to an analog feedback signal (Z3); a summing device (5) for solving the difference between the input signal (ZA) and the feedback signal (Z3); a filter (6) for filtering the difference signal (Z1); and a clocked quantizing device (7) for quantizing the filtered difference signal (Z2) into a digital output signal (ZD) with the bit width N.

Abstract: A multi-bit sigma/delta converter for converting an analog input signal into a digital output signal comprises a filter device for filtering the analog input signal which is added to a feedback signal to form an intermediate signal. An integrator device for integrating the filtered intermediate signal added to an inner feedback signal forms a quantizer input signal. A quantizer device quantizes the quantizer input signal to form the digital output signal. An inner feedback digital/analog converter is provided for converting the digital output signal directly into the inner feedback signal. A DEM device for performing dynamic element matching on the digital output signal and providing a matched digital signal is provided and a feedback digital/analog converter for converting the matched digital signal into the feedback signal is implemented.

Abstract: The invention relates to a power-saving multibit delta-sigma converter (1) comprising: an input (2) for an analog input signal (ZA) and an output (3) for a digital output signal (ZD); a digital-to-analog converter (4) having a bit width N and serving to convert the digital output signal (ZD) to an analog feedback signal (Z3); a summing device (5) for solving the difference between the input signal (ZA) and the feedback signal (Z3); a filter (6) for filtering the difference signal (Z1); and a clocked quantizing device (7) for quantizing the filtered difference signal (Z2) into a digital output signal (ZD) with the bit width N.

Abstract: A receiver circuit for receiving an analog signal comprises a mixer device, a first integrator device coupled to the mixer device, a second integrator device following the first integrator device, a quantizer device, and first and second feedback digital/analog converters. The mixer device mixes the analog signal with a local-oscillator frequency and outputs a mixer current signal. The first integrator device generates a first intermediate signal by integrating the mixer current signal summed with a first feedback current signal, the second integrator device generates a quantizer input signal by integrating the first intermediate signal summed with a second feedback current signal, and the quantizer device generates a digital output signal by quantizing the quantizer input signal.

Abstract: A multi-bit sigma/delta converter for converting an analog input signal into a digital output signal comprises a filter device for filtering the analog input signal which is added to a feedback signal to form an intermediate signal. An integrator device for integrating the filtered intermediate signal added to an inner feedback signal forms a quantizer input signal. A quantizer device quantizes the quantizer input signal to form the digital output signal. An inner feedback digital/analog converter is provided for converting the digital output signal directly into the inner feedback signal. A DEM device for performing dynamic element matching on the digital output signal and providing a matched digital signal is provided and a feedback digital/analog converter for converting the matched digital signal into the feedback signal is implemented.

Abstract: The control apparatus (8?) is used to dynamically assign N individual references to N individual comparators of a quantizer in a sigma-delta analogue/digital converter, the control apparatus (8?) generating a digital control signal (9?). The control apparatus (8?) has a storage means (12) for providing the value of the control signal (9?) at the time k?1, and a summation means (10) for summing the output signal Y of the quantizer with the stored value of the first control signal (9?) at the time k?1.

Abstract: In a method for starting a circuit arrangement an output signal of a circuit arrangement which comprises interlinked feedback control circuits is utilized as a control variable for the feedback control circuits and an input signal for the circuit arrangement is damped for a predetermined time period during a starting phase of the circuit arrangement.