Abstract: A sigma-delta converter is disclosed. In one embodiment, the sigma-delta converter includes two series-connected converter stages which are each supplied with a feedback signal, a comparator stage which is connected downstream of the second converter stage, which is supplied with the output signal from the second converter stage and which provides an at least two-value comparator signal, and at least one output stage which has at least one digital integrator and which produces a multibit signal as output signal.

Abstract: The control apparatus (8?) is used to dynamically assign N individual references to N individual comparators of a quantizer in a sigma-delta analogue/digital converter, the control apparatus (8?) generating a digital control signal (9?). The control apparatus (8?) has a storage means (12) for providing the value of the control signal (9?) at the time k?1, and a summation means (10) for summing the output signal Y of the quantizer with the stored value of the first control signal (9?) at the time k?1.

Abstract: The invention relates to a forward-amplifying filter circuit which has an analogue filter with poles and zero points, having a first number of integrators which form the poles, which are arranged in series with one another and which each have an active component with a capacitance arranged in parallel therewith, having a second number of coefficients which form the zero points and which have at least one forward-amplifying path which contains a differentiating element, having a summing node whose input side is connected to the forward-amplifying paths of the zero points and whose output side is connected to the input of the last of the active components arranged in series. The invention also relates to an analog/digital converter circuit having such a filter circuit.

Abstract: A sigma-delta converter is disclosed. In one embodiment, the sigma-delta converter includes two series-connected converter stages which are each supplied with a feedback signal, a comparator stage which is connected downstream of the second converter stage, which is supplied with the output signal from the second converter stage and which provides an at least two-value comparator signal, and at least one output stage which has at least one digital integrator and which produces a multibit signal as output signal.

Abstract: A quantizer for a sigma delta modulator comprising at least one preliminary stage V1, V2), the quantizer quantizing an input signal (EQ) present at it in accordance with at least one threshold signal (yth,i) and outputting it as a result value (yQ) at a digital result output (OUT), wherein the quantizer has a number of comparators (5j) corresponding to the number of threshold signals (yth,j), which compare the input signal (EQ) with the respective threshold signal (yth,j), the threshold signal being reduced or increased by a correction voltage (ydac3) or a correction current, the correction voltage or correction current being generated in accordance with the result value (yQ) output at the result output (OUT).

Abstract: A circuit configuration for metering pulse recognition includes an A/D converter that receives a signal containing metering pulses, and a digital comparator circuit for comparing the output signal from the A/D converter with a reference value. A detector unit evaluates the output signal from the comparator circuit. This means that an analog comparator can be dispensed with, and the chip area and the development complexity can be reduced.

Abstract: The invention relates to a quantizer (1) for a sigma delta modulator (10) having at least one input stage (2), the quantizer quantizing an input signal (21) present at its input stage in accordance with at least one threshold signal and outputting it as result value (22) at a digital result output (23). Furthermore, the invention relates to a sigma delta modulator having such a quantizer.

Abstract: The invention relates to an electric circuit for generating a periodic signal comprising: a capacitor device which has a first terminal and a second terminal; a signal node that is connected, via a first signal having a first period is applied; a discharging device that is connected, via a third switching device, to the first terminal and, via a fourth switching device, to the second terminal, whereby the second terminal, via a fifth switching device, and the first terminal, via a sixth switching device, are connected to a first reference potential; and comprising a clock pulse generating device for receiving the first signal and for generating a first switch clock pulse, a second switch clock pulse, and the periodic signal. The first and the second switch clock pulse do not overlap and are inverse with regard to one another.

Abstract: The invention relates to a forward-amplifying filter circuit which has an analogue filter with poles and zero points, having a first number of integrators which form the poles, which are arranged in series with one another and which each have an active component with a capacitance arranged in parallel therewith, having a second number of coefficients which form the zero points and which have at least one forward-amplifying path which contains a differentiating element, having a summing node whose input side is connected to the forward-amplifying paths of the zero points and whose output side is connected to the input of the last of the active components arranged in series. The invention also relates to an analog/digital converter circuit having such a filter circuit.

Abstract: The invention relates to a quantizer 1 for a sigma delta modulator 10 having at least one input stage 2, the quantizer quantizing an input signal 21 present at its input stage in accordance with at least one threshold signal and outputting it as result value 22 at a digital result output 23. Furthermore, the invention relates to a sigma delta modulator having such a quantizer.

Abstract: A quantizer for a sigma delta modulator comprising at least one preliminary stage V1, V2), the quantizer quantizing an input signal (EQ) present at it in accordance with at least one threshold signal (yth,i) and outputting it as a result value (yQ) at a digital result output (OUT), wherein the quantizer has a number of comparators (5j) corresponding to the number of threshold signals (yth,j), which compare the input signal (EQ) with the respective threshold signal (yth,j) , the threshold signal being reduced or increased by a correction voltage (ydac3) or a correction current, the correction voltage or correction current being generated in accordance with the result value (yQ) output at the result output (OUT).