Abstract: An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections.

Abstract: The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. In many applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 ?H, and must have an equivalent series resistance of less than 0.1 ?. For this reason, those inductors are always bulky components, of a typical size of 2×2×1 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 very-high DC resistance values.

Abstract: An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimized for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.

Abstract: A planar inductive unit having at least one operating frequency is provided. The inductive unit comprises at least one inductor winding (120) having a first width (121) and a centre (122) and being arranged in a first plane. The inductive unit furthermore comprises at least one ground path (200) having a first section (205) extending in the first plane and at least a second section (210) with a second width (211) extending in at least a second plane.

Abstract: The invention relates to a field-effect transistor having a higher efficiency than the known field-effect transistors, in particular at higher operating frequencies. This is achieved by electrically connecting sources of a plurality of main current paths by means of a strap line (SL) being inductively coupled to a gate line (Gtl) and/or a drain line (Drnl) for forming an additional RF-return current path parallel to the RF-return current path in a semiconductor body (SB). The invention further relates to a field-effect transistor package, a power amplifier, a multi-stage power amplifier and a base station comprising such a field-effect transistor.

Abstract: Magnetic shield layout (10, 10 A-10 G) arranged for an integrated circuit of a semiconductor device comprising at least a first inductor (1) having a first crosssectional inductor-area (11), and at least a second inductor (2) having a second crosssectional inductor-area (12), wherein the inductor-areas (11, 12) are located in an inductor-plane (P) and wherein the first and second inductors (1, 2) in operation are subject to an induction coupling; at least one magnetic shield (20) for reducing the induction coupling, said magnetic shield having a conductive path (21) marking a first crosssectional shield-area (13) assigned to the first cross-sectional inductor-area (11) and a second crosssectional shield-area (14) assigned to the second crosssectional inductor-area (12); wherein the shield-areas (13, 14) are conductively and continuously connected by the conductive path (21) such that in operation a magnetic field generated by the first inductor (1) is largely cancelled by the magnetic field of the second cros

Abstract: Typically, chips nowadays comprise a number of circuits as well as a number of inductors, often RF-inductors. These IC inductors are essential to realize the voltage controlled oscillators needed in the many fully integrated transceiver chips, serving a multitude of wireless communication protocols, that are provided to the market today. The present invention relates to an RF-IC packaging method, which virtually eliminates the long-range electromagnetic crosstalk between inductors and transmission lines of different parts of the circuitry.

Abstract: The invention relates to a planar inductive component (11) comprising at least a first and a second concentric inductor, which include a first and a second spiral pattern (12A, 12B), respectively. Both spiral patterns have a first end point (13A, 13B) and a second end point (14A, 14B), are electrically interconnected, interlaced, and interrupted at the outer side, and provided with two contacts (16A, 16B) on one side of the opening (15A, 15B) and two contacts (17A, 17B) on the other side of the opening (15A, 15B). By interconnecting the first two contacts (16A, 16B) and the second two contacts (17A, 17B), respectively, both spiral patterns are connected in parallel. The spiral patterns (12A, 12B), which are magnetically coupled, have identical electrical and magnetic properties. This leads to a reduction of eddy current losses at high frequencies. This results in a planar inductive component (11) which is suitable for high-frequency operation with a high maximum quality factor Q.

Abstract: A planar inductor (50) comprises a conductive path in the form of a spiral pattern (53A-53D, 54A-54D). A conductive connecting path (62A, 63) connects a terminal (60) to an intermediate tap point (61A). The connecting path comprises at least one path portion which is radially directed with respect to the spiral pattern (53A-53D). The connecting path (62A, 63) can be routed via the inside of the spiral pattern. Where the connecting path comprises only radially-directed path portions, they are commonly joined at the centre (64) of the spiral pattern. Multiple path portions (62A, 62B) can each connect to the intermediate tap point of a respective conductive path. The connecting path can use a further conductive track (85) which is parallel to the conductive path which forms the spiral pattern.

Abstract: Consistent with an example embodiment, there is a method for calibrating an N terminal microwave measurement network. The method including the measurement of network parameter values of a load device depends on the knowledge of the parasitic impedance of the load device. According to the example embodiment, the accuracy of the method is improved by at least approximately determining the parasitic impedances of the load device. This may be achieved by measuring network parameter values of an auxiliary open device, having substantially identical parasitic impedance as that of the load device. The accuracy is further increased by measuring network parameter values of an auxiliary short device, having substantially identical parasitic impedance as that of the load device. A similar principle can be used for de-embedding a device under test. A load device, an auxiliary open device and an auxiliary short device each having substantially identical parasitic impedances are disclosed.

Abstract: The accuracy of a method for calibrating an N terminal microwave measurement network (10), the method comprising the measurement of network parameter values of a load device (43), depends on the knowledge of the parasitic impedance of the load device (43). According to the invention, the accuracy of the method is improved by at least approximately determining the parasitic impedances of the load device (43). In one embodiment this is achieved by measuring network parameter values of an auxiliary open device (44), having a substantially identical parasitic impedance as the load device (43). The accuracy is further increased by measuring network parameter values of an auxiliary short device (45), having a substantially identical parasitic impedance as the load device (43). A similar principle can be used for de-embedding a device under test. A load device (43), an auxiliary open device (44) and an auxiliary short device (45) having substantially identical parasitic impedances are disclosed.

Abstract: The invention relates to a planar inductive component (11) comprising at least a first and a second concentric inductor, which include a first and a second spiral pattern (12A, 12B), respectively. Both spiral patterns have a first end point (13A, 13B) and a second end point (14A, 14B), are electrically interconnected, interlaced, and interrupted at the outer side, and provided with two contacts (16A, 16B) on one side of the opening (15A, 15B) and two contacts (17A, 17B) on the other side of the opening (15A, 15B). By interconnecting the first two contacts (16A, 16B) and the second two contacts (17A, 17B), respectively, both spiral patterns are connected in parallel. The spiral patterns (12A, 12B), which are magnetically coupled, have identical electrical and magnetic properties. This leads to a reduction of eddy current losses at high frequencies. This results in a planar inductive component (11) which is suitable for high-frequency operation with a high maximum quality factor Q.