Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.

Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.

Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Abstract: A method and an apparatus for detecting a number of variation in resistance within a material stack in response to a scanning and injection of a non-contacting electron stream into a material stack, the material stack having a first conductive contact layer, a variable resistive layer, a fixed resistive layer, and a second conductive contact layer, and the variations in resistance within the material stack being based on one of a plurality of resistive states of the variable resistive layer. The method also includes generating two magnetic fields within a transformer, the transformer being operatively coupled to the first and second conductive contact layers and generating a differential output signal within the transformer based on the two magnetic fields, the differential output signal being associated with one of the plurality of resistive states.