Patents by Inventor Luke A. Johnson

Luke A. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160146973
    Abstract: A method of processing geological data is provided for input to a geostatistical modelling algorithm to predict a value for a parameter relating to a physical property of the Earth. An input data set corresponding to a measured geological parameter is processed to determine a characteristic function of the input data with respect to a geological measure. The input data is transformed to reduce spatial bias with respect to the geological distance measure by applying an inverse function. A statistical weighting is calculated for the transformation and the transformation and weighting are used to predict a representative value of the physical property corresponding to the measured geological parameter. A data processing apparatus and computer program product are also provided.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 26, 2016
    Applicant: Cognitive Geology Limited
    Inventor: Luke Johnson
  • Publication number: 20160127155
    Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.
    Type: Application
    Filed: June 27, 2013
    Publication date: May 5, 2016
    Inventors: Luke A. JOHNSON, Sleiman BOU SLEIMAN
  • Patent number: 9318953
    Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Chia How Low, Luke A. Johnson, Mun Fook Leong
  • Patent number: 9280162
    Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Luke A. Johnson, Adhiveeraraghavan Srikanth, Wenjun Yun
  • Publication number: 20150347341
    Abstract: Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 3, 2015
    Inventor: Luke A. Johnson
  • Publication number: 20150248134
    Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.
    Type: Application
    Filed: March 31, 2015
    Publication date: September 3, 2015
    Inventors: Luke A. JOHNSON, Adhiveeraraghavan SRIKANTH, Wenjun YUN
  • Patent number: 9009366
    Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Luke A. Johnson, Adhiveeraraghavan Srikanth, Wenjun Yun
  • Publication number: 20140258568
    Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.
    Type: Application
    Filed: March 25, 2014
    Publication date: September 11, 2014
    Inventors: Luke A. JOHNSON, Adhiveeraraghavan SRIKANTH, Wenjun YUN
  • Publication number: 20140232710
    Abstract: Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.
    Type: Application
    Filed: March 22, 2012
    Publication date: August 21, 2014
    Inventors: Chia How Low, Luke A. Johnson, Mun Fook Leong
  • Patent number: 8683098
    Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: March 25, 2014
    Assignee: Intel Corporation
    Inventors: Luke A. Johnson, Adhiveeraraghavan Srikanth, Wenjun Yun
  • Patent number: 8253440
    Abstract: Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: August 28, 2012
    Assignee: Intel Corporation
    Inventors: John Maddux, Luke A. Johnson, Ronald W. Swartz, Donald Rush, Meetul Goyal, Rajashri Doddamani
  • Publication number: 20110238868
    Abstract: Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Inventors: Luke A. Johnson, Adhiveeraraghavan Srikanth, Wenjun Yun
  • Patent number: 7974174
    Abstract: A method and an apparatus for detecting a number of variation in resistance within a material stack in response to a scanning and injection of a non-contacting electron stream into a material stack, the material stack having a first conductive contact layer, a variable resistive layer, a fixed resistive layer, and a second conductive contact layer, and the variations in resistance within the material stack being based on one of a plurality of resistive states of the variable resistive layer. The method also includes generating two magnetic fields within a transformer, the transformer being operatively coupled to the first and second conductive contact layers and generating a differential output signal within the transformer based on the two magnetic fields, the differential output signal being associated with one of the plurality of resistive states.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: July 5, 2011
    Assignee: Intel Corporation
    Inventors: Michael A. Brown, Luke A. Johnson
  • Publication number: 20110076375
    Abstract: An ice cube machine that generates ice cubes having an alcohol content of at least 2-5%. The ice cube machine operates at temperatures of no greater than 0° F., and typically at least 0° F. or colder. An ice dispensing system monitors the amount of ice cubes dispensed from the machine and can determine the amount of alcohol dispensed from the system.
    Type: Application
    Filed: December 7, 2010
    Publication date: March 31, 2011
    Inventors: Luke Johnson, Bruce Johnson, Joseph Robinson, Brandon Mathiowetz
  • Publication number: 20110050280
    Abstract: Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 3, 2011
    Inventors: John Maddux, Luke A. Johnson, Ronald W. Swartz, Donald Rush, Meetul Goyal, Rajashri Doddamani
  • Publication number: 20100249375
    Abstract: A method for selectively orienting molecules on a surface of a solid support. The method includes: (a) attaching a linker molecule to the surface of the solid support, the linker molecule including a head group that is capable of binding to the solid support, and a tail group that is capable of chelating to a metal ion; (b) subsequently treating the solid support with a solution containing the metal ion; (c) attaching a metal ion chelating tag to the molecules to form tagged molecules; and (d) capturing the tagged molecules on the solid support by contacting it with the tagged molecules to form a monolayer of molecules on the surface of the solid support in which a majority of the molecules are held in the same orientation with respect to the surface.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 30, 2010
    Applicant: TACNIA PTY LTD
    Inventors: Lisandra Lorraine Martin, Daniel Luke Johnson
  • Patent number: 7759114
    Abstract: A method for selectively orienting molecules on a surface of a solid support. The method includes the steps of: (a) attaching a linker molecule to the surface of the solid support, the linker molecule including a head group that is capable of binding to the solid support, and a tail group that is capable of chelating to a metal ion; (b) subsequently treating the solid support with a solution containing the metal ion; (c) attaching a metal ion chelating tag to the molecules to form tagged molecules; and (d) capturing the tagged molecules on the solid support by contacting it with the tagged molecules to form a monolayer of molecules on the surface of the solid support in which a majority of the molecules are held in the same orientation with respect to the surface. The invention also provides a sensor chip formed using the methods of the invention.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: July 20, 2010
    Assignee: Tacnia Pty Ltd
    Inventors: Lisandra Lorraine Martin, Daniel Luke Johnson
  • Patent number: 7656226
    Abstract: An embodiment may be described as a switched capacitor analog equalizer circuit with offset voltage cancellation, where an embodiment comprises an amplifier in which a feedback path from its output port to one of its input ports is provided during a reset phase, and where the amplifier's input port connected to the feedback path is also connected to one terminal of an offset-correction capacitor and one terminal of a sampling capacitor. The other terminal of the offset-correction capacitor is connected to a switch and the other terminal of the sampling capacitor is connected to an input port to receive a signal. During the reset phase, the switch is open, and during a sampling phase, the switch is closed so that the offset-correction capacitor and the sampling capacitor are connected in parallel. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Luke A Johnson, Yueming He
  • Patent number: 7649388
    Abstract: In an embodiment, an analog voltage recovery circuit comprising a plurality of capacitors having first terminals connected to a node having the analog voltage, and comprising a state machine, where during an operating mode the second terminals of the plurality of capacitors are coupled to a first rail, and where during a digitization mode the state machine couples the second terminals of a set of the plurality of capacitors to a second rail so that the analog voltage is closer to the second rail voltage than during the beginning of the digitization mode. In an embodiment, the analog voltage recovery circuit brings the node voltage to the second rail voltage at the end of the digitization mode, and then floats the node and couples the second terminals of the plurality of capacitors to the first rail to approximately restore the analog voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: January 19, 2010
    Assignee: Intel Corporation
    Inventors: Luke A. Johnson, Yueming He
  • Publication number: 20090188116
    Abstract: An ergonomic scraper, such as a floor scraper using a standard replaceable blade, is provided. Embodiments include a scraper having an elongated handle, a scraper head for fixedly holding a blade mounted to a first end of the handle, an upper hand grip at a second end of the handle, and a lower hand grip between the first and second ends of the handle. The handle has an S-shape to reduce the angle between the blade and a workpiece. A pair of wheels is mounted near the scraper head for easily adjusting the blade attack angle. The scraper head is adjustable for changing the scraping angle of the blade to suit the user and/or the job.
    Type: Application
    Filed: January 30, 2009
    Publication date: July 30, 2009
    Inventors: Gary E. van Deursen, David W. Kaiser, Luke Johnson