Abstract: A special roller machine for a metal polar plate. A box body is a square with a circular through hole in the middle part. Upper and lower pressing rollers are mounted in the circular through hole; the upper and lower pressing rollers are mounted in grooves formed in the lower sides of upper and lower sector rotating bodies through bearing seats and are connected with upper and lower rotating blocks respectively; the rotating blocks are symmetrically arranged and are connected with upper and lower servo electric cylinders through connecting rod mechanisms respectively, then the pressing rollers are finely adjusted; four identical arch-shaped plates are mounted on the inner surface of the circular through hole for locating the rotating blocks; and main transmission is implemented in such a way that a servo motor drives the lower pressing roller to move through a safety coupling, a reduction gearbox and a cross coupling.

Abstract: A special roller machine for a metal polar plate. A box body is a square with a circular through hole in the middle part. Upper and lower pressing rollers are mounted in the circular through hole; the upper and lower pressing rollers are mounted in grooves formed in the lower sides of upper and lower sector rotating bodies through bearing seats and are connected with upper and lower rotating blocks respectively; the rotating blocks are symmetrically arranged and are connected with upper and lower servo electric cylinders through connecting rod mechanisms respectively, then the pressing rollers are finely adjusted; four identical arch-shaped plates are mounted on the inner surface of the circular through hole for locating the rotating blocks; and main transmission is implemented in such a way that a servo motor drives the lower pressing roller to move through a safety coupling, a reduction gearbox and a cross coupling.

Abstract: The present invention provides a method and a device for predicting the change in the water cut rising rate of a water-drive oil reservoir. The method comprises: determining the actual water cut rising rates and water cuts of the oil reservoir, plotting the scatter plot of the actual water cut rising rates and water cuts of the oil reservoir; fitting the scatter plot of the actual water cut rising rates and water cuts of the oil reservoir to a relationship between the water cut rising rate and the water cut, to obtain the initial water cut of the oil reservoir, the degree of recovery of crude oil when the water cut of the oil reservoir is the initial water cut, the ultimate recovery of crude oil when the water cut of the oil reservoir is the water cut limit; and determining the law of change in the water cut rising rate with respect to the degree of recovery and the change in the water cut rising rate in the water-drive oil reservoir.

Abstract: An online programming education method and system, comprising choosing and acquiring an online course for a piece of knowledge; and completing a programming exercise in relation to the piece of knowledge and, if the completed programming exercise meets a predetermined criterion, proceeding to an online course for another piece of knowledge next to said piece of knowledge. After the user has learnt a piece of knowledge, a programming exercise in relation thereto is provided to ensure that another piece of knowledge next to said piece of knowledge will not be made available unless the completed programming exercise meets a predetermined criterion, i.e., unless the user has mastered the piece of knowledge to some extent. Further, a teacher can use the teacher terminal to answer the user's questions in an online manner, thus enhancing his/her learning efficiency.

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract: One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed.

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract: Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

Abstract: Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract: Thermal oxidation treatment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device with at least one cavity etched into the device; performing a thermal oxidation treatment to the at least one cavity; and cleaning the at least one cavity. One process includes, for instance: providing a semiconductor device with a substrate, at least one layer over the substrate and at least one fin; forming at least one gate over the fin; doping at least one region below the fin; applying a spacer layer over the device; etching the spacer layer to expose at least a portion of the gate material; etching a cavity into the at least one fin; etching a shaped opening into the cavity; performing thermal oxidation processing on the at least one cavity; and growing at least one epitaxial layer on an interior surface of the cavity.

Abstract: Generally, the present disclosure is directed to methods for forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements. One illustrative method disclosed herein includes performing a thermal oxidation process to form a layer of thermal oxide material on a semiconductor layer of a semiconductor substrate, and forming a plurality of openings in the layer of thermal oxide material to form a plurality of isolation regions from the layer of thermal oxide material, wherein each of the plurality of openings exposes a respective surface region of the semiconductor layer.