Patents by Inventor Lun Zhao

Lun Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140124794
    Abstract: Generally, the present disclosure is directed to methods for forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements. One illustrative method disclosed herein includes performing a thermal oxidation process to form a layer of thermal oxide material on a semiconductor layer of a semiconductor substrate, and forming a plurality of openings in the layer of thermal oxide material to form a plurality of isolation regions from the layer of thermal oxide material, wherein each of the plurality of openings exposes a respective surface region of the semiconductor layer.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: Globalfoundries Inc.
    Inventors: Tong Weihua, Krishnan Bharat, Lun Zhao, Kim Seung, Lee Yongmeng, Kim Sun
  • Patent number: 7443039
    Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: October 28, 2008
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin
  • Publication number: 20060197223
    Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.
    Type: Application
    Filed: December 23, 2005
    Publication date: September 7, 2006
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin
  • Patent number: 7005370
    Abstract: A method for manufacturing an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: February 28, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin
  • Publication number: 20050253262
    Abstract: A method for manufacturng an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.
    Type: Application
    Filed: May 13, 2004
    Publication date: November 17, 2005
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Lun Zhao, Wan Looi, Kyaw Aung, Yonggang Jin, Jae-Yong Song, Won Shin