Patents by Inventor Lung-En Kuo

Lung-En Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140367798
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20140322883
    Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
    Type: Application
    Filed: July 15, 2014
    Publication date: October 30, 2014
    Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
  • Publication number: 20140308761
    Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20140306272
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Patent number: 8853015
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Patent number: 8816409
    Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: August 26, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
  • Patent number: 8691652
    Abstract: A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Hsuan-Hsu Chen
  • Publication number: 20140038417
    Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 6, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Chih Lin, Hsuan-Hsu Chen, Jiunn-Hsiung Liao, Lung-En Kuo
  • Publication number: 20130295738
    Abstract: A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed.
    Type: Application
    Filed: May 3, 2012
    Publication date: November 7, 2013
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Hsuan-Hsu Chen
  • Patent number: 8524608
    Abstract: The present invention provides a method for fabricating a patterned structure in a semiconductor device, which includes the following processes. First, a target layer, a first mask and a first patterned mask are sequentially formed on a substrate. Then, a first etching process is performed to form a plurality of characteristic structures on the substrate, wherein each of the characteristic structures comprises a patterned first mask and a patterned target layer. A second patterned mask is formed on the substrate, wherein the second patterned mask covers a portion of the characteristic structures and exposes a predetermined region. A second etching process is performed to fully eliminate the characteristic structures within the predetermined region. Finally, a third etching process is performed to fully eliminate the target layer not covered by the patterned first mask.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: September 3, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Hsuan-Hsu Chen, Meng-Chun Lee
  • Publication number: 20130093062
    Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Inventors: Ying-Chih Lin, Hsuan-Hsu Chen, Jiunn-Hsiung Liao, Lung-En Kuo
  • Patent number: 8329594
    Abstract: A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material layer.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: December 11, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Lung-En Kuo
  • Publication number: 20120034781
    Abstract: A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material layer.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 9, 2012
    Inventor: Lung-En Kuo
  • Publication number: 20120012904
    Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
  • Patent number: 7851370
    Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: December 14, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Min-Chieh Yang
  • Patent number: 7709275
    Abstract: A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: May 4, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Min-Chieh Yang, Lung-En Kuo
  • Publication number: 20090258500
    Abstract: A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Inventors: Min-Chieh Yang, Lung-En Kuo
  • Publication number: 20090081817
    Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Min-Chieh Yang