Patents by Inventor Lung-En Kuo
Lung-En Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881409Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.Type: GrantFiled: June 28, 2021Date of Patent: January 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hao Huang, Chun-Lung Chen, Kun-Yuan Liao, Lung-En Kuo, Chia-Wei Hsu
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Publication number: 20240006525Abstract: A method for manufacturing a high electron mobility transistor device includes providing a substrate. A channel material, a barrier material, a polarization adjustment material and a conductive material are formed on the substrate. A hard mask layer is formed on the conductive material. The conductive material is patterned to form a conductive layer by using the hard mask layer as a mask. A plurality of protection layers is formed on sidewalls of the hard mask layer and the conductive layer. The polarization adjustment material is patterned to form a polarization adjustment layer by using the plurality of protection layers and the hard mask as masks. The plurality of protection layers is removed. A portion of the conductive layer is laterally removed to form a first gate conductive layer.Type: ApplicationFiled: July 21, 2022Publication date: January 4, 2024Applicant: United Microelectronics Corp.Inventors: Yuan Yu Chung, Bo-Yu Chen, You-Jia Chang, Lung-En Kuo, Kun-Yuan Liao, Chun-Lung Chen
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Publication number: 20230112917Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.Type: ApplicationFiled: October 31, 2021Publication date: April 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Chang, Kun-Yuan Liao, Lung-En Kuo, Chih-Tung Yeh
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Publication number: 20230006041Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a plurality of nanowires. The substrate has an upper surface. The nanowires are stacked on the upper surface of the substrate along a first direction. The nanowires include a triangle in a cross section, and the nanowires include a plane extending along a second direction, a first down-slant facet on a (111) plane, and a second down-slant facet on an additional (111) plane.Type: ApplicationFiled: July 27, 2021Publication date: January 5, 2023Inventors: Jing-Wen HUANG, Wei-Hao HUANG, Chung-Yi CHIU, Lung-En KUO, Kun-Yuan LIAO
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Publication number: 20220384200Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.Type: ApplicationFiled: June 28, 2021Publication date: December 1, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hao Huang, Chun-Lung Chen, Kun-Yuan Liao, Lung-En Kuo, Chia-Wei Hsu
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Publication number: 20200111802Abstract: A method of preventing charge loss from a floating gate includes providing a substrate comprising a memory cell region and a logic region, wherein a floating gate is disposed in the memory cell region and a gate structure is disposed within the logic region, a first hard mask covers the floating gate and a second hard mask covers the first hard mask. A planarization process is performed to remove entirely the second hard mask and expose the first hard mask. Later, a third hard mask is formed to cover the first hard mask, the gate structure and the substrate, wherein the third hard mask prevents charges in the floating gate from flowing to the first hard mask. Finally, the third hard mask within the logic region is removed and the third hard mask remains within the memory region.Type: ApplicationFiled: October 4, 2018Publication date: April 9, 2020Inventors: Nan-Yuan Huang, Cheng-Lin Peng, Lung-En Kuo, Li-Chieh Hsu
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Patent number: 10164052Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.Type: GrantFiled: August 3, 2017Date of Patent: December 25, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Fu Hsu, Chun-Mao Chiou, Shih-Chieh Hsu, Lung-En Kuo, You-Di Jhang, Jian-Cun Ke
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Publication number: 20170330954Abstract: A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer.Type: ApplicationFiled: August 3, 2017Publication date: November 16, 2017Inventors: Chia-Fu Hsu, Chun-Mao Chiou, Shih-Chieh Hsu, Lung-En Kuo, You-Di Jhang, Jian-Cun Ke
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Patent number: 9761690Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.Type: GrantFiled: July 4, 2014Date of Patent: September 12, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Fu Hsu, Chun-Mao Chiou, Shih-Chieh Hsu, Lung-En Kuo, You-Di Jhang, Jian-Cun Ke
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Patent number: 9711368Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.Type: GrantFiled: April 15, 2013Date of Patent: July 18, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
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Patent number: 9455176Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.Type: GrantFiled: March 17, 2016Date of Patent: September 27, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Lung-En Kuo, Chien-Ting Lin, Shih-Fang Tzou
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Publication number: 20160197005Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.Type: ApplicationFiled: March 17, 2016Publication date: July 7, 2016Inventors: Po-Chao Tsao, Lung-En Kuo, Chien-Ting Lin, Shih-Fang Tzou
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Patent number: 9385206Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.Type: GrantFiled: October 22, 2015Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Fu Hsu, Chun-Mao Chiou, Shih-Chieh Hsu, Jian-Cun Ke, Chun-Lung Chen, Lung-En Kuo
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Publication number: 20160043195Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.Type: ApplicationFiled: October 22, 2015Publication date: February 11, 2016Inventors: Chia-Fu Hsu, Chun-Mao Chiou, Shih-Chieh Hsu, Jian-Cun Ke, Chun-Lung Chen, Lung-En Kuo
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Publication number: 20150357430Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.Type: ApplicationFiled: July 4, 2014Publication date: December 10, 2015Inventors: Chia-Fu Hsu, Chun-Mao Chiou, Shih-Chieh Hsu, Lung-En Kuo, You-Di Jhang, Jian-Cun Ke
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Patent number: 9196699Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; depositing a liner on the gate structure and the substrate; and performing an etching process by injecting a gas comprising CH3F, O2, and He for forming a spacer adjacent to the gate structure.Type: GrantFiled: July 11, 2014Date of Patent: November 24, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Fu Hsu, Chun-Mao Chiou, Shih-Chieh Hsu, Jian-Cun Ke, Chun-Lung Chen, Lung-En Kuo
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Patent number: 9117909Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.Type: GrantFiled: August 28, 2014Date of Patent: August 25, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
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Patent number: 9093473Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.Type: GrantFiled: July 15, 2014Date of Patent: July 28, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
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Publication number: 20150206759Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.Type: ApplicationFiled: January 21, 2014Publication date: July 23, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Lung-En Kuo, Chien-Ting Lin, Shih-Fang Tzou
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Patent number: 9013024Abstract: A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.Type: GrantFiled: October 15, 2013Date of Patent: April 21, 2015Assignee: United Microelectronics Corp.Inventors: Ying-Chih Lin, Hsuan-Hsu Chen, Jiunn-Hsiung Liao, Lung-En Kuo