Patents by Inventor Lyle E. Adams

Lyle E. Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12639213
    Abstract: A module identifier and a request address associated with an access request are received at a host memory buffer (HMB) access module in a solid-state drive (SSD) system. A translated address is determined based at least in part on the module identifier and the request address, including by accessing at least one translation table that stores address mappings between (1) a plurality of processors in the SSD system and (2) a host memory buffer; each processor in the plurality of processors has a non-overlapping memory space in the host memory buffer. The access request is performed at a host interface, including by accessing the host memory buffer using the translated address, wherein the host memory buffer is located in host memory that is external to the SSD system.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: May 26, 2026
    Assignee: Nanjing Tenafe Electronic Technology Co., Ltd.
    Inventors: Lyle E. Adams, Chen Xiu
  • Publication number: 20250328463
    Abstract: A module identifier and a request address associated with an access request are received at a host memory buffer (HMB) access module in a solid-state drive (SSD) system. A translated address is determined based at least in part on the module identifier and the request address, including by accessing at least one translation table that stores address mappings between (1) a plurality of processors in the SSD system and (2) a host memory buffer; each processor in the plurality of processors has a non-overlapping memory space in the host memory buffer. The access request is performed at a host interface, including by accessing the host memory buffer using the translated address, wherein the host memory buffer is located in host memory that is external to the SSD system.
    Type: Application
    Filed: July 20, 2023
    Publication date: October 23, 2025
    Inventors: Lyle E. Adams, Chen Xiu
  • Patent number: 12346601
    Abstract: A hardware-implemented, pre-sequence execution checker is used to receive a set of firmware instructions that includes a suspend command, an intervening command, and a resume command, wherein the suspend command and the resume command are associated with suspending and resuming a same command, respectively; access a configurable conditions table that includes whether the suspend command and the resume command are supported by a storage media device; access state information that includes whether said same command has completed; and determine whether to perform or skip the suspend command based at least in part on the configurable conditions table and the state information. If it is determined to perform the suspend command, the suspend command and the intervening command are output. If it is determined to skip the suspend command, the intervening command is output.
    Type: Grant
    Filed: March 21, 2023
    Date of Patent: July 1, 2025
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Wanqiang Zhang
  • Patent number: 12346610
    Abstract: A storage controller system includes a host command module that manages communication with a host and a backend command module that manages communication with a storage system. A storage interface hardware functional module, in response to an unsuccessful or successful operation, generates a first or second type of a status message with an automated retry flag set to TRUE or FALSE. A virtual queue module receives the status message and selects a virtual queue. If (1) the flag being set to TRUE and (2) independent of the queue ID, an original command virtual queue is selected. If (1) the flag being set to FALSE and (2) the queue ID being set to the value associated with the backend command module, a virtual queue associated with the backend command module is selected. A stored message in the selected virtual queue is provided to the selected message recipient.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: July 1, 2025
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Zhikai Chen, Lyle E. Adams
  • Patent number: 12314185
    Abstract: For each data in a plurality of data, data is read from a cache unit. For each data in the plurality of data, a group to which the data read from the cache unit belongs to is determined based at least in part on a predetermined grouping rule. A determination is made of (1) a quantity of groups and (2) a quantity of data corresponding to each group after determining the groups to which the plurality of data belong. Data belonging to a same group is written into a contiguous storage space of the cache unit, including by: sequentially reading the plurality of data from the cache unit and sequentially writing the plurality of data into the cache unit.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: May 27, 2025
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Meng Kun Lee, Chen Xiu, Weitao Xu, Lyle E. Adams
  • Patent number: 12259831
    Abstract: Configuration information is sent from a configuration controller to a processor module in a System On Chip (SOC) and associated with firmware. In response to receiving the configuration information, context switching associated with an interrupt pin in the processor module is disabled. Hardware state information is sent from a hardware functional module in the SOC to the interrupt pin. In response to receiving the hardware state information, the processor module determines, based at least in part on the hardware state information and after completing any active firmware operations per the disabled context switching, a response. The response is received at a responding module and the responding module performs a process associated with the response.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: March 25, 2025
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams, Haibo Zhu
  • Publication number: 20250045227
    Abstract: In response to receiving an indication to re-synchronize a first local credit a first message associated with clearing the first local credit is sent to a message sender implemented on the SOC. The first local credit is associated with flow control from the message sender to the first hardware functional module; the first masked credit is based at least in part on the first local credit and a first re-synchronization register and is independent of a second re-synchronization register associated with the second hardware functional module. In response to receiving the first message from the first hardware functional module, the first local credit is updated to be the zero value. If the message sender has a message to send, the message is sent if the first local credit has a non-zero value or is retained if the first local credit has a zero value.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams
  • Patent number: 12197364
    Abstract: A storage controller implemented on a System On Chip (SOC) includes an upstream functional module, a host interface, a logical to physical (L2P) interface, and a message inspection engine. The configured message inspection engine is obtained using one or more configuration settings and receives an input message from the upstream functional module. The input message is analyzed to determine a retention plan, a content modification plan, and a destination control plan. An output message is generated based at least in part on the input message, the content modification plan, and the destination control plan. If there is an affirmative content modification decision, the output message is populated with content absent from the input message. If there is an affirmative destination modification decision, the output message is populated with a destination absent from the input message. The output message is output unless there is an affirmative retention decision.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: January 14, 2025
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams
  • Patent number: 12197356
    Abstract: If a first group selection setting is set to TRUE, an NVM Express (NVMe) processor sends a first set of NVMe status information that includes a transfer data end event. If a second group selection setting is set to TRUE, the NVMe processor sends a second set of NVMe status information that includes an NVMe error event. A firmware functional module sends firmware status information. The aggregation module aggregates and timestamps the first and second sets of NVMe status information, if any, and the firmware status information to obtain a timestamped and aggregated message stream that is output by an interface. The timestamped and aggregated message stream enables a visualization system to analyze the NVMe processor and the firmware functional module. The NVMe processor, firmware functional module, aggregation module, and interface are in a storage controller, implemented on a system on chip (SOC), that manages a storage medium.
    Type: Grant
    Filed: January 29, 2024
    Date of Patent: January 14, 2025
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Meng Kun Lee, Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Xiaojun Ding
  • Patent number: 12153533
    Abstract: A storage controller system includes a hardware functional module, implemented in hardware on a System On Chip (SOC), that: in response to receiving a synchronization trigger, sends, to a message sender, a first message that includes a value for a local credit. The local credit is associated with flow control. In response to receiving the first message from the hardware functional module, the message sender updates the local credit with the value that is included in the first message. If the message sender has a second message to send, the message sender determines whether the local credit has a non-zero value or a zero value; if the local credit has the non-zero value, the second message is sent. If the local credit has a zero value, the second message is retained. A storage interface, implemented on the SOC, communicates with storage media via an associated channel.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: November 26, 2024
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams
  • Patent number: 12124873
    Abstract: A hardware functional module performs a given task. A first notification that the given task has completed and which includes a scoreboard identifier is sent to a scoreboard module. The scoreboard module selects a scoreboard counter based on the scoreboard identifier. The selected scoreboard counter is incremented. It is determined whether the selected scoreboard counter exceeds a corresponding scoreboard threshold. If the selected scoreboard counter exceeds the corresponding scoreboard threshold, a second notification indicating that the plurality of tasks has completed is sent. If the scoreboard identifier corresponds to the host command module, the second notification is sent to the host command module. If the scoreboard identifier corresponds to the backend command module, the second notification is sent to the backend command module.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: October 22, 2024
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Deqiang Yang
  • Publication number: 20240168897
    Abstract: If a first group selection setting is set to TRUE, an NVM Express (NVMe) processor sends a first set of NVMe status information that includes a transfer data end event. If a second group selection setting is set to TRUE, the NVMe processor sends a second set of NVMe status information that includes an NVMe error event. A firmware functional module sends firmware status information. The aggregation module aggregates and timestamps the first and second sets of NVMe status information, if any, and the firmware status information to obtain a timestamped and aggregated message stream that is output by an interface. The timestamped and aggregated message stream enables a visualization system to analyze the NVMe processor and the firmware functional module. The NVMe processor, firmware functional module, aggregation module, and interface are in a storage controller, implemented on a system on chip (SOC), that manages a storage medium.
    Type: Application
    Filed: January 29, 2024
    Publication date: May 23, 2024
    Inventors: Meng Kun Lee, Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Xiaojun Ding
  • Publication number: 20240143532
    Abstract: A storage controller implemented on a System On Chip (SOC) includes an upstream functional module, a host interface, a logical to physical (L2P) interface, and a message inspection engine. The configured message inspection engine is obtained using one or more configuration settings and receives an input message from the upstream functional module. The input message is analyzed to determine a retention plan, a content modification plan, and a destination control plan. An output message is generated based at least in part on the input message, the content modification plan, and the destination control plan. If there is an affirmative content modification decision, the output message is populated with content absent from the input message. If there is an affirmative destination modification decision, the output message is populated with a destination absent from the input message. The output message is output unless there is an affirmative retention decision.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams
  • Publication number: 20240134810
    Abstract: A storage controller system includes a hardware functional module, implemented in hardware on a System On Chip (SOC), that: in response to receiving a synchronization trigger, sends, to a message sender, a first message that includes a value for a local credit. The local credit is associated with flow control. In response to receiving the first message from the hardware functional module, the message sender updates the local credit with the value that is included in the first message. If the message sender has a second message to send, the message sender determines whether the local credit has a non-zero value or a zero value; if the local credit has the non-zero value, the second message is sent. If the local credit has a zero value, the second message is retained. A storage interface, implemented on the SOC, communicates with storage media via an associated channel.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams
  • Publication number: 20240134689
    Abstract: A hardware functional module performs a given task. A first notification that the given task has completed and which includes a scoreboard identifier is sent to a scoreboard module. The scoreboard module selects a scoreboard counter based on the scoreboard identifier. The selected scoreboard counter is incremented. It is determined whether the selected scoreboard counter exceeds a corresponding scoreboard threshold. If the selected scoreboard counter exceeds the corresponding scoreboard threshold, a second notification indicating that the plurality of tasks has completed is sent. If the scoreboard identifier corresponds to the host command module, the second notification is sent to the host command module. If the scoreboard identifier corresponds to the backend command module, the second notification is sent to the backend command module.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 25, 2024
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Deqiang Yang
  • Publication number: 20240111460
    Abstract: A storage controller system includes a host command module that manages communication with a host and a backend command module that manages communication with a storage system. A storage interface hardware functional module, in response to an unsuccessful or successful operation, generates a first or second type of a status message with an automated retry flag set to TRUE or FALSE. A virtual queue module receives the status message and selects a virtual queue. If (1) the flag being set to TRUE and (2) independent of the queue ID, an original command virtual queue is selected. If (1) the flag being set to FALSE and (2) the queue ID being set to the value associated with the backend command module, a virtual queue associated with the backend command module is selected. A stored message in the selected virtual queue is provided to the selected message recipient.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 4, 2024
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Zhikai Chen, Lyle E. Adams
  • Patent number: 11921654
    Abstract: A hardware functional module sends, to an aggregation module and in a standardized message format, first status information associated with the hardware functional module according to a first set of reporting rules via a first dedicated link. The firmware functional module sends, to the aggregation module and in the standardized message format, second status information associated with the firmware functional module according to a second set of reporting rules via a second dedicated link. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and inserts a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream enables a visualization system to analyze the hardware functional module and the firmware functional module.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: March 5, 2024
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Meng Kun Lee, Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Xiaojun Ding
  • Patent number: 11907147
    Abstract: A message inspection engine, implemented in hardware in a System on Chip (SOC), is configured using configuration information to obtain a configured message inspection engine. An input message is received at the configured message inspection engine from an upstream functional module in the SOC. The configured message inspection engine is used to analyze the input message to determine a content modification plan and a destination control plan and to generate an output message based at least in part on the input message, the content modification plan, and the destination control plan, including by populating the output message with a downstream functional module specified by the destination control plan. The output message is output from the configured message inspection engine.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: February 20, 2024
    Assignee: Beijing Tenafe Electronic Technology Co., Ltd.
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams
  • Patent number: 11899984
    Abstract: A message that includes a queue identifier (ID) is received from a first hardware functional module. A virtual queue is selected from a plurality of virtual queues in a shared queue structure based at least in part on the queue ID and configurable message handling settings(s). The message is stored in the selected virtual queue and a message recipient is selected from a plurality of potential message recipients based at least in part on the configurable message handling setting(s), where the plurality of potential message recipients includes the second hardware functional module and the processor module. The message is provided to the selected message recipient.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: February 13, 2024
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Zhikai Chen, Lyle E. Adams
  • Patent number: 11899601
    Abstract: A synchronization trigger associated with synchronizing credit is obtained at a message receiver in a System On Chip (SOC). In response to receiving the synchronization trigger, a value for a local credit in the message sender is sent from the message receiver to a message sender in the SOC. At the message sender, the local credit is updated with the value for the credit that is received from the message receiver, wherein a requirement to send a message from the message sender to the message receiver is that the local credit has a non-zero value.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: February 13, 2024
    Inventors: Priyanka Nilay Thakore, Lyle E. Adams