Patents by Inventor Lyle E. Adams

Lyle E. Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200293476
    Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Publication number: 20200264984
    Abstract: An entry is read from a first memory component, the entry associated with a first logical address. The first entry includes a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component. The segment of the logical-to-physical address map includes a second entry associated with the first logical address. A second physical address is written to the second entry in the first memory component based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component.
    Type: Application
    Filed: September 3, 2019
    Publication date: August 20, 2020
    Inventors: Lyle E. ADAMS, Sheng BI, Karl D. SCHUH, Pushpa SEETAMRAJU, Dan Z. TUPY, Yongcai XU
  • Patent number: 10705996
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 7, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Publication number: 20200201568
    Abstract: A method is described, which includes receiving, by firmware of a memory subsystem, a memory request that requests access to a set of memory components managed by a hardware controller of the memory subsystem and transmitting a sub-request in response to receipt of the memory request. The method further includes receiving, by the firmware from the hardware controller, status information describing the current operating state of the hardware controller at the time of receipt of the sub-request, wherein the status information is transmitted by the hardware controller in response to the sub-request and determining, by the firmware, whether the status information indicates that the hardware controller is operating under an exception condition.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Kihoon Park, Lyle E. Adams
  • Publication number: 20200192844
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Application
    Filed: November 25, 2019
    Publication date: June 18, 2020
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Patent number: 10521383
    Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 31, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
  • Patent number: 7275120
    Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: September 25, 2007
    Inventors: Michael Ou, Lyle E. Adams, Edward Yan
  • Patent number: 7191268
    Abstract: Described herein are methods and systems for conducting computer system communications with a number of different devices that communicate with the computer system in a number of different protocols via a protocol-shared combination host controller. Combination host controller has a reduced set of pins for handling communication in a plurality of communication protocols. The total number of pins needed for driving communication in a plurality of communication protocols is reduced by sharing at least one control pin or at least one data pin or combination thereof between at least some of the plurality of communication protocols. In one embodiment, data communications in different protocols overlapping in time can be interleaved onto to a shared data path by suspending a current transmission until a later higher priority transmission is complete.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 13, 2007
    Inventors: Lyle E. Adams, Andrew Weir
  • Patent number: 7191256
    Abstract: Described herein are methods and systems for conducting computer system communications with a number of different devices that communicate with the computer system in a number of different protocols via a protocol-shared combination host controller. Combination host controller has a reduced set of pins for handling communication in a plurality of communication protocols. The total number of pins needed for driving communication in a plurality of communication protocols is reduced by sharing at least one control pin or at least one data pin or combination thereof between at least some of the plurality of communication protocols. In one embodiment, data communications in different protocols overlapping in time can be interleaved onto to a shared data path by suspending a current transmission until a later higher priority transmission is complete.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: March 13, 2007
    Inventors: Lyle E. Adams, Andrew Weir
  • Patent number: 7124376
    Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: October 17, 2006
    Assignee: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Stephen Chappell, Savitha Gandikota, Jon Udell, Brian Gutcher, Jef Munsil
  • Patent number: 7062587
    Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) and the DMA peripheral(s) using a Memory Access Controller (MAC) and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: June 13, 2006
    Assignee: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Hussam I. Ramlaoui, Billy D. Mills, Robin Bhagat
  • Publication number: 20040267972
    Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.
    Type: Application
    Filed: May 14, 2004
    Publication date: December 30, 2004
    Applicant: Palmchip Corporation
    Inventors: Michael Ou, Lyle E. Adams, Edward Yan
  • Patent number: 6769046
    Abstract: A system resource router interfaces initiators through protocol-adapting sockets to a plurality of sub-buses. A switch matrix allows at least some of the sockets to be connected to two or more of the sub-buses. Each sub-bus interfaces through a channel controller to target devices like memory and peripherals. A graphical user interface, assembly program, and computer-aided design platform allow users to customize system resource router configurations for particular applications. At least one embodiment produces Verilog or other hardware description language intellectual property technology libraries. It implements the optimal mix of sub-buses, switches, sockets, and controllers that will be needed for a particular user application.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: July 27, 2004
    Assignee: Palmchip Corporation
    Inventors: Lyle E. Adams, Billy D. Mills
  • Publication number: 20040022107
    Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) the MAC, and the DMA peripheral(s) using a single centralized address decoder and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.
    Type: Application
    Filed: July 28, 2003
    Publication date: February 5, 2004
    Applicant: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Hussam I. Ramlaoui, Billy D. Mills, Robin Bhagat
  • Publication number: 20040010652
    Abstract: An SOC architecture that provides a latency tolerant protocol for internal bus signals is disclosed. The SOC includes at least a processor core and one or more peripherals that communicate on a first internal bus that carries signals having a latency tolerant signal protocol that enables an arbitrary number of pipeline stages between any signal initiator and any signal target. A shared memory subsystem, DMA-type peripherals, and a second internal bus with a topology overlapping the first bus, may also be included. All signals over both busses are point-to-point and registered and all transactions on both busses are handshaked. An arbitrary number of flip-flops, multiplexing routers, and/or decoding routers may be included between any signal initiator and any signal target on either bus, and may be added at any time during the design and layout of the SOC.
    Type: Application
    Filed: June 24, 2003
    Publication date: January 15, 2004
    Applicant: Palmchip Corporation
    Inventors: Lyle E. Adams, Ronald H. Nicholson, S. Jauher A. Zaidi
  • Patent number: 6601126
    Abstract: A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: July 29, 2003
    Assignee: Palmchip Corporation
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Hussam I. Ramlaoui, Billy D. Mills, Robin Bhagat
  • Publication number: 20020038401
    Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.
    Type: Application
    Filed: September 17, 2001
    Publication date: March 28, 2002
    Inventors: S. Jauher A. Zaidi, Michael Ou, Lyle E. Adams, Stephen Chappell, Savitha Gandikota, Jon Udell, Brian Gutcher, Jef Munsil
  • Publication number: 20010042147
    Abstract: A system resource router interfaces initiators through protocol-adapting sockets to a plurality of sub-buses. A switch matrix allows at least some of the sockets to be connected to two or more of the sub-buses. Each sub-bus interfaces through a channel controller to target devices like memory and peripherals. A graphical user interface, assembly program, and computer-aided design platform allow users to customize system resource router configurations for particular applications. At least one embodiment produces Verilog or other hardware description language intellectual property technology libraries. It implements the optimal mix of sub-buses, switches, sockets, and controllers that will be needed for a particular user application.
    Type: Application
    Filed: December 5, 2000
    Publication date: November 15, 2001
    Inventors: Lyle E. Adams, Billy D. Mills
  • Patent number: 5978954
    Abstract: An on-the-fly error detection and correction hardware core for a mass storage hard disk drive comprises a microcode machine optimized and limited to doing Galois Field arithmetic (GF[2.sub.8 ]) in support of Reed-Solomon error detection and correction (RS-EDC). The microcode machine is implemented as a hardware core in a system-on-a-chip design that includes a general purpose core RISC-processor. A dual-input arithmetic logic unit (ALU) includes a set of basic arithmetic blocks necessary to support the RS-EDC operations, i.e., a multiplier, a dedicated adder, a general purpose adder, a divider, a log unit, a quadratic solution lookup, a cubic solution lookup, and a move datapath. The operations and outputs of all the basic arithmetic blocks are presented in parallel to an op-code selector. The selected output is routed back for deposit to one of eight general purpose registers (R0-R7).
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: November 2, 1999
    Assignee: Palmchip Corporation
    Inventors: Michael Ou, Lyle E. Adams, S. Jauher A. Zaidi, Hussam I. Ramlaoui