Patents by Inventor Lyle E. Adams
Lyle E. Adams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230033116Abstract: Firmware instruction(s) are selected from a plurality of firmware instructions based at least in part on: (1) a conditions table that includes one or more conditions for handling the plurality of firmware instructions and (2) state information. It is determined how to handle the one or more selected firmware instructions based at least in part on: (1) the conditions table and (2) the state information. In the event the determined handling is to perform the selected firmware instructions, an instruction sequence is obtained, from a sequencing table that includes one or more instruction sequences associated with a storage media device, based at least in part on the one or more selected firmware instructions. In the event the determined handling is to perform the one or more selected firmware instructions, the obtained instruction sequence is output to the storage media device.Type: ApplicationFiled: July 15, 2022Publication date: February 2, 2023Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Wanqiang Zhang
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Publication number: 20230034009Abstract: In response to receiving an exception indication, an exception-handling state variable in state information is asserted. Firmware instruction(s) are selected from a plurality of firmware instructions based at least in part on: (1) a conditions table that includes condition(s) for handling the plurality of firmware instructions and (2) the state information that includes the exception-handling state variable. It is determined how to handle the selected firmware instruction(s) based at least in part on: (1) the conditions table and (2) the state information that includes the exception-handling state variable where. The plurality of firmware instructions includes: (1) a non-exception-handling set of firmware instruction(s) and (2) an exception-handling set of firmware instruction(s).Type: ApplicationFiled: July 15, 2022Publication date: February 2, 2023Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Wanqiang Zhang
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Publication number: 20230035289Abstract: Central processing units (CPUs) are configured to support host access instruction(s) that are associated with accessing solid state storage. A resource management module, implemented independently of the CPUs, receives a resource allocation request that includes a usage type identifier and requested amount of a resource, where the usage type identifier is associated with a group identifier. Adjustable resource configuration information is accessed to obtain: (1) a maximum associated with the usage type identifier, (2) a minimum associated with the usage type identifier, and (3) a group limit associated with the group identifier. Resource state information is accessed and it is determine whether to grant the request based at least in part on the maximum, minimum, group limit, and resource state information. The resource allocation request is then granted or denied based on the determination.Type: ApplicationFiled: January 31, 2022Publication date: February 2, 2023Inventors: Priyanka Nilay Thakore, Lyle E. Adams, Chen Xiu
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Publication number: 20230022281Abstract: A system on chip (SOC) system includes functional modules, including a first and second functional module. The first and second functional module are configured to send, to an aggregation module and in a standardized message format, first and second status information associated with the first and second functional module according to a first and second set of one or more reporting rules, respectively. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and insert a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream is stored and enables a visualization system to analyze the first functional module and the second functional module.Type: ApplicationFiled: June 30, 2022Publication date: January 26, 2023Inventors: Meng Kun Lee, Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Xiaojun Ding
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Patent number: 11544210Abstract: A system on chip (SOC) system includes functional modules, including a first and second functional module. The first and second functional module are configured to send, to an aggregation module and in a standardized message format, first and second status information associated with the first and second functional module according to a first and second set of one or more reporting rules, respectively. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and insert a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream is stored and enables a visualization system to analyze the first functional module and the second functional module.Type: GrantFiled: June 30, 2022Date of Patent: January 3, 2023Inventors: Meng Kun Lee, Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Xiaojun Ding
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Patent number: 11513959Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.Type: GrantFiled: February 25, 2021Date of Patent: November 29, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Horia C. Simionescu, Lyle E. Adams, Yongcai Xu, Mark Ish
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Patent number: 11481348Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.Type: GrantFiled: January 28, 2021Date of Patent: October 25, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
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Patent number: 11277355Abstract: A resource allocation request that includes a usage type identifier and requested amount of a resource is received where the usage type identifier is associated with a group identifier. Adjustable resource configuration information is accessed to obtain: (1) a maximum associated with the usage type identifier, (2) a minimum associated with the usage type identifier, and (3) a group limit associated with the group identifier. Resource state information is accessed and it is determined whether to grant the resource allocation request based at least in part on the maximum, the minimum, the group limit, and the resource state information. If so, the resource allocation request is granted. If not, the resource allocation request is denied.Type: GrantFiled: July 27, 2021Date of Patent: March 15, 2022Inventors: Priyanka Nilay Thakore, Lyle E. Adams, Chen Xiu
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Publication number: 20210182227Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.Type: ApplicationFiled: January 28, 2021Publication date: June 17, 2021Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
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Publication number: 20210182199Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.Type: ApplicationFiled: February 25, 2021Publication date: June 17, 2021Inventors: Horia C. SIMIONESCU, Lyle E. ADAMS, Yongcai XU, Mark ISH
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Patent number: 10942879Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.Type: GrantFiled: May 28, 2020Date of Patent: March 9, 2021Assignee: MICRON TECHNOLOGY, INC.Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
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Patent number: 10936496Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.Type: GrantFiled: June 7, 2019Date of Patent: March 2, 2021Assignee: MICRON TECHNOLOGY, INC.Inventors: Horia C. Simionescu, Lyle E. Adams, Yongcai Xu, Mark Ish
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Publication number: 20200387449Abstract: A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.Type: ApplicationFiled: June 7, 2019Publication date: December 10, 2020Inventors: Horia C. SIMIONESCU, Lyle E. ADAMS, Yongcai XU, Mark ISH
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Publication number: 20200293476Abstract: A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
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Publication number: 20200264984Abstract: An entry is read from a first memory component, the entry associated with a first logical address. The first entry includes a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component. The segment of the logical-to-physical address map includes a second entry associated with the first logical address. A second physical address is written to the second entry in the first memory component based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component.Type: ApplicationFiled: September 3, 2019Publication date: August 20, 2020Inventors: Lyle E. ADAMS, Sheng BI, Karl D. SCHUH, Pushpa SEETAMRAJU, Dan Z. TUPY, Yongcai XU
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Patent number: 10705996Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.Type: GrantFiled: November 25, 2019Date of Patent: July 7, 2020Assignee: MICRON TECHNOLOGY, INC.Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
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Publication number: 20200201568Abstract: A method is described, which includes receiving, by firmware of a memory subsystem, a memory request that requests access to a set of memory components managed by a hardware controller of the memory subsystem and transmitting a sub-request in response to receipt of the memory request. The method further includes receiving, by the firmware from the hardware controller, status information describing the current operating state of the hardware controller at the time of receipt of the sub-request, wherein the status information is transmitted by the hardware controller in response to the sub-request and determining, by the firmware, whether the status information indicates that the hardware controller is operating under an exception condition.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Kihoon Park, Lyle E. Adams
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Publication number: 20200192844Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.Type: ApplicationFiled: November 25, 2019Publication date: June 18, 2020Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
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Patent number: 10521383Abstract: A first operation identifier is assigned to a first operation directed to a memory component, the first operation identifier having an entry in a first data structure that associates the first operation identifier with a first plurality of buffer identifiers. It is determined whether the first operation collides with a prior operation assigned a second operation identifier, the second operation identifier having an entry in the first data structure that associates the second operation identifier with a second plurality of buffer identifiers. It is determined whether the first operation is a read or a write operation. In response to determining that the first operation collides with the prior operation and that the first operation is a read operation, the first plurality of buffer identifiers are updated with a buffer identifier included in the second plurality of buffer identifiers.Type: GrantFiled: December 17, 2018Date of Patent: December 31, 2019Assignee: MICRON TECHNOLOGY, INC.Inventors: Lyle E. Adams, Mark Ish, Pushpa Seetamraju, Karl D. Schuh, Dan Tupy
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Patent number: 7275120Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.Type: GrantFiled: May 14, 2004Date of Patent: September 25, 2007Inventors: Michael Ou, Lyle E. Adams, Edward Yan