Patents by Inventor Lynne M. Gignac

Lynne M. Gignac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10386409
    Abstract: One or more contacts are detected in an electron microscope image corresponding to a region of interest on an integrated circuit. One or more standard cells are identified based on the detected one or more contacts in the electron microscope image. One or more components of the integrated circuit are determined based on the identified one or more standard cells.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lynne M. Gignac, Chung-Ching Lin, Franco Stellari
  • Publication number: 20190248654
    Abstract: A membrane is electrically charged to a polarity. A surface of carbon nanotubes (CNTs) in a solution is caused to acquire a charge of the polarity. The solution is filtered through the membrane. An electromagnetic repulsion between the membrane of the polarity and the CNTs of the polarity causes the CNTs to spontaneously align to form a crystalline structure.
    Type: Application
    Filed: February 14, 2018
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Abram L. Falk, Damon B. Farmer, Lynne M. Gignac
  • Publication number: 20170074927
    Abstract: One or more contacts are detected in an electron microscope image corresponding to a region of interest on an integrated circuit. One or more standard cells are identified based on the detected one or more contacts in the electron microscope image. One or more components of the integrated circuit are determined based on the identified one or more standard cells.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: Lynne M. Gignac, Chung-Ching Lin, Franco Stellari
  • Patent number: 8889546
    Abstract: A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Patent number: 8866257
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Ll, Ping-Chaun Wang
  • Patent number: 8823176
    Abstract: An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Publication number: 20140177373
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin LI, Ping-Chuan Wang
  • Patent number: 8716071
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Patent number: 8679970
    Abstract: A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac
  • Patent number: 8535991
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Publication number: 20120329271
    Abstract: A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.
    Type: Application
    Filed: August 31, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Patent number: 8133767
    Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu
  • Publication number: 20110092031
    Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 21, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu
  • Patent number: 7893520
    Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu
  • Publication number: 20100118636
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Application
    Filed: January 15, 2010
    Publication date: May 13, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Publication number: 20100084767
    Abstract: An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 8, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu, Surbhi Mittal
  • Publication number: 20090289365
    Abstract: A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 26, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lynne M. Gignac
  • Publication number: 20090278229
    Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 12, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lynne M. Gignac, Chao-Kun Hu
  • Publication number: 20090045484
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Patent number: 6979393
    Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ? or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Jr., Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke