Abstract: A logic circit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

Abstract: A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

Abstract: Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for non-cacheable devices are not in that predetermined range. Since by definition cacheable devices are 32-bit devices, pipelined operation is allowed only if the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are non-cacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: A microprocessor system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

Abstract: A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS precharge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.

Abstract: A new class of sulfonated 2-(2'-hydroxyaryl)-2H-benzotriazole compounds and method for using them and other sulfonated hydroxyaryl benzotriazoles on nylon fibers to improve stain resistance and dye lightfastness has been discovered. A process is provided for improving stain resistance of nylon fibers by treatment with sulfonated aromatic-formaldehyde condensate and fluorinated dry soil resist agents.

Abstract: A holder for a liquid-containing carton, for example a milk carton, comprises a body adapted to fit over the top of the carton, the body having resiliently-mounted abutments which snap into engagement beneath exposed edges of a top closure of the carton. A pouring spout is rotatably mounted on the body and includes a blade which cuts a circular pouring opening in the closure upon rotation of the spout, the spout being sealed with in the opening. The body includes a handle by which the carton can be carried and tipped to dispense the contents.

Abstract: In a self-contained battery powered keyboard entry device, the keyboard is driven from a microprocessor and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter. The sense lines are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode.

Abstract: A source of relatively high air pressure is connected to a pressure regulator which provides a lower relatively uniform predetermined pressure to a plurality of tires on wheels of a vehicle. If the pressure in any one of the tires drop below the others, the pressure from the regulator automatically brings it up to the uniform pressure.

Abstract: This invention relates generally to the cooling of liquid-cooled devices such as engines, motors, transformers, and similar heat-producing or energy-conversion machines, that are designed to operate within specified temperature ranges.

Abstract: A hook member for securing and snugging a door of a structure such as a barn is provided with a cam lever which may be manually rotated after the hook member is engaged with a latch bar on the door to move the hook member longitudinally away from the door and thus pull the door snugly against the portion of the structure on which the hook member is mounted. The cam hooks of the invention may be mounted inside a building to snug the rear edge portions of single or double sliding doors against the building wall, or to snug the front edge portion of a single sliding door or of a hinged door against the jamb; and may also be used to snug the forward edges of a pair of double sliding doors together either from the inside or from the outside.