Abstract: The present disclosure relates to a method of treating a neoplastic condition in a subject in need thereof. This method involves administering to the subject a combination therapy comprising (i) an aminothiol-conjugate of Formula (I): wherein Core, Linker, R1, R2, R3, m, n, and p are as described above. The present disclosure also relates to methods of treating a subject in need of antimicrobial treatment, methods of increasing sensitivity of a cell to treatment with an anti-neoplastic drug or antimicrobial drug, and combination therapeutics comprising one or more aminothiol-conjugates of Formula (I).

Abstract: Anti-RSV antibodies with neutralizing potency against RSV subtype A and RSV subtype B are provided, as well as methods for their identification, isolation, generation, and methods for their preparation and use are provided.

Abstract: A method of broadening epitopic coverage of an antigen of interest, wherein a first sample of the antigen of interest is contacted with a first plurality of host cells collectively expressing a first library of antibodies. Host cells expressing antibodies that bind to the antigen are then collected from among the first plurality of host cells, and a composition is prepared comprising a polyclonal mixture of antibodies expressed by these host cells. A second sample of the antigen of interest is then contacted with an aliquot of the prepared composition and a second plurality of host cells collectively expressing a second library of antibodies. Host cells expressing antibodies that bind to the second sample of the antigen are then collected from among the second plurality of host cells.

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

Abstract: A multi-layered pillow protector includes a first panel; a second panel that is perimetrically joined to the first panel such that the inner surfaces of the first panel and the second panel define a cavity having a void volume configured for the disposal of a pillow from one side; a plurality of appended panels adjoined externally along one of the sides of the first panel and the second panel with the rest of the sides of each of the appended panels independently accessible to move to form a plurality of layers on the first panel and second panel; and each of the plurality of appended panels can be interchangeably used as head resting surfaces by flipping over the first and second panels.

Abstract: Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.

Abstract: There are provided a system and a method for maintaining the integrity of a memory component that includes receiving, by a memory controller, a plurality of memory requests including at least one write request, allocating a data block into a buffer cache to cache the at least one write request, detecting whether sufficient time has elapsed beyond a predetermined threshold, in response to sufficient time having elapsed beyond the predetermined threshold, flagging a backend memory as being available; and in response to the flagging, fetching the at least one write request to write data to the memory component.

Abstract: There are provided a system and a method for write or store driven buffer cache memory for a Reliable Array of Independent Disks (RAID)-protected memory. For example, there is provided a system that can include a RAID subsystem configured to maintain the integrity of a section of a memory. The system can further include a buffer memory communicatively coupled to the RAID subsystem. And the RAID subsystem may be configured to limit a frequency of RAID access memory command amplification by accessing the buffer memory the subsystem is performing an operation configured to maintain the integrity of the section of the memory.

Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

Abstract: Anti-RSV antibodies with neutralizing potency against RSV subtype A and RSV subtype B are provided, as well as nucleic acid sequences encoding such antibodies, methods for their identification, isolation, generation, and methods for their preparation and use are provided.

Abstract: An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

Abstract: The present invention provides, among other things, methods and compositions for diagnosing and/or treating cancer by targeting CCR8. In particular, the present invention provides technologies for depleting Treg cells, and particularly tumor-infiltrating Treg cells.

Abstract: A processing device, operatively coupled with a memory device, retrieves data from the memory device for merging at one or more sectors of a cache line in a cache, wherein the cache line comprises a plurality of sectors. The processing device determines, based on one or more bits associated with each sector of the cache line, whether each sector of the cache line is configured with at least one of a write protection mode and enable mode, respectively. The processing device writes the data from the memory device to each sector of the cache line using the at least one of the write protection mode or the enable mode.

Abstract: A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).