Abstract: A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor and an NPN bipolar transistor. The method includes applying an erase voltage, e.g. +20 volts, to each of the Y sense lines while maintaining each of the X sense lines at this erase voltage and each of the X write lines at ground and applying the erase voltage to each of the source lines such that each of the PMOS transistors assumes a relatively negative threshold state. The method includes applying a write voltage e.g., +20 volts, to selected X write lines while maintaining unselected X write and selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage e.g., +10 volts, which is less than the write voltage, and maintaining each of the X sense lines at an intermediate voltage e.g.

Abstract: A process and structure are disclosed which are suitable for forming large arrays of Schottky diodes at desired locations between mutually perpendicular strips of aluminum and strips of metal-silicide. The invention is particularly useful in creating read-only memories and programmable logic arrays, and allows fabrication of Schottky diodes more compactly than previous structures.

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Abstract: A process for fabricating an electrically erasable nonvolatile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically-isolated relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped regions of a second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon regions of the first conductivity type are formed on the first insulating region and on the second relatively lightly doped epitaxial region.

Abstract: A method for fabricating insulating regions in an integrated circuit structure is disclosed in which the insulating regions do not encroach upon the surrounding integrated circuit and in which a substantially planar surface across the top of the insulating material and the substrate is created. The method includes the steps of removing portions of the substrate wherever the insulating regions are to be formed, beginning to deposit insulating material across the substrate and in the openings created, and, while continuing to deposit insulating material simultaneously removing insulating material from generally horizontal surfaces and redepositing it on generally vertical surfaces of the substrate and the openings until a planar surface results.

Abstract: A process for fabricating integrated injection logic structures including both vertical and lateral bipolar transistors in oxide isolated pockets of silicon includes the steps of forming a patterned composite silicon nitride-silicon dioxide layer to serve as a transistor emitter and self-aligned base mask, and introducing desired impurities to form the lateral transistor emitter and collector. The mask is partially removed and additional impurities introduced to form the vertical transistor base and vertical transistor collector.The process does not require the use of vapor deposited silicon dioxide to pattern the wafer surface, and therefore reduces pinhole defects and the encroachment of the field oxidation on the epitaxial silicon pocket in which devices are formed. The process also results in a flatter topography to allow more uniform and reliable metal interconnections.

Abstract: An NPN transistor, a P channel and an N channel field effect transistor are formed in the same epitaxial layer on a monolithic semiconductor substrate. Subcollector-like areas of one conductivity type are diffused into selected regions of a semiconductor substrate of the opposite conductivity type. Each subcollector-like area comprises two impurities of the same conductivity type but different concentrations and diffusion rates. An epitaxial layer of the same conductivity type as the substrate is grown over the substrate. One of each pair of subcollector impurities outdiffuses completely through the epitaxial layer during the growth of the epitaxial layer and during subsequent heat treatments to define a plurality of isolated pockets of a conductivity type opposite the conductivity type of the surrounding epitaxial layer and substrate. An NPN bipolar transistor and a P channel field effect transistor subsequently are formed in respective isolated pockets.

Abstract: A solid state analog image sensor is disclosed in which the video input to the sensor is stored as a charge on a floating gate in a cell. The cell itself consists of a single J-FET with Schottky barrier contact to the metal word line. All associated address and drive/sense circuits are located around the active cell area. By filling up the active area with only the J-FET's and relegating the rest of the circuitry to the peripheral, inactive region, high picture resolution is obtained.

Abstract: in a field effect transistor having a semiconductor body, spaced source and drain regions, an insulating layer on the surface of the body, and an electrode to the source region, the improvement being a field shield electrode on the insulating layer overlying at least the PN junction of the drain region that terminates at the interface of the surface of the body and the insulating layer, and a gate electrode on the insulating layer over at least a portion of the channel region, the gate electrode and the field shield electrode in combination overlying all of the channel region. Another feature of the invention is a high voltage line for use on a semiconductor device consisting of a diffused region of opposite conductivity in the semiconductor body, an overlying insulating layer having an opening therein, and an overlying field shield conductive stripe that overlies the PN junction of the diffused region that terminates at the surface of the body.