Abstract: An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.

Abstract: An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.

Abstract: A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. Pass/fail testing may be used for identifying whether the IC is good or bad, and additional diagnostic testing using additional cycles may be used for disabling faulty ports or correcting inverted address bits. The test method may be implemented as a function test or as a memory built-in self-test. The test method may be used during manufacturing test or during function design verification.

Abstract: A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. Pass/fail testing may be used for identifying whether the IC is good or bad, and additional diagnostic testing using additional cycles may be used for disabling faulty ports or correcting inverted address bits. The test method may be implemented as a function test or as a memory built-in self-test. The test method may be used during manufacturing test or during function design verification.

Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.

Abstract: An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.

Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure

Abstract: A method includes preferentially placing fill regions adjacent to transistors of a particular conductivity type, such as p-channel transistors, for a plurality of standard cell instances of a device design. The method also includes evaluating all transistors of the first conductivity type prior to evaluating any transistors of a second conductivity type. The second conductivity type is opposite the first conductivity type. For each transistor being evaluated, it is determined whether a criterion is me. A fill region is placed within a field isolation region adjacent to the transistor if the criterion is met.

Abstract: An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line.

Abstract: A method of designing a data processing device design includes determining thermal profile information to indicate a predicted operating temperature for a device instance in the design. The device instance is associated with a first library cell having a relatively high threshold voltage characteristic. A cost function value is determined for the device instance based on the thermal profile information and based on timing information for data paths associated with the device instance. Based on the cost function value, the library cell associated with the device instance can be changed to a cell having a higher threshold voltage characteristic.

Abstract: A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.

Abstract: A method implemented at a computer aided design tool includes preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances. Preferentially placing the fill regions includes preferentially placing the fill regions adjacent to transistors of a first conductivity type as compared to placing the fill regions adjacent to transistors of a second conductivity type that is opposite the first conductivity type.

Abstract: A method of designing a data processing device design includes determining thermal profile information to indicate a predicted operating temperature for a device instance in the design. The device instance is associated with a first library cell having a relatively high threshold voltage characteristic. A cost function value is determined for the device instance based on the thermal profile information and based on timing information for data paths associated with the device instance. Based on the cost function value, the library cell associated with the device instance can be changed to a cell having a higher threshold voltage characteristic.

Abstract: A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.

Abstract: A method of testing critical delay paths of an integrated circuit design is disclosed. The method includes predicting and ranking a set of critical delay paths based on a set of predicted delay characteristics. Integrated circuits based on the integrated circuit design are tested to determine a set of actual delay measurements for the critical delay paths. The critical delay paths are ranked based on the actual delay measurements, and the results are correlated to the predicted ranking of critical delay paths to produce a confidence measurement that measures the likelihood that the actual critical delay paths of the design have been tested for a given production batch of devices.

Abstract: A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.

Abstract: A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In particular, the simulator simulates transitions from a first set of circuit nodes to a second set of circuit nodes selected from the plurality of circuit nodes, the simulating based on executing a first set of simulation events. A second set of simulation events is then generated in response to executing the first set of simulation events. During the simulation, a time is computed for each of the transitions. An an event scheduling diagram is constructed during simulation. The event scheduling diagram depicts the transitions and the times of the transitions.

Abstract: A method and device for determining memory element and intermediate point correspondences between design models is disclosed. The method includes developing graph representations of two circuit design models of an electronic device. The circuit design models each include input and output nodes corresponding to input and output nodes of the electronic device. The circuit design models also include memory and intermediate nodes corresponding to memory elements and intermediate points, respectively of the electronic device. An intermediate point represents a point between memory elements of the electronic device, and so can represent logic gates or other modules of the device. Memory elements and intermediate points can be referred to collectively as circuit elements. Nodes in the graph representation represent inputs, outputs, memory elements or intermediate points in the design models. A correspondence between the circuit elements in circuit design models is determined based on the graph representations.

Abstract: A method of testing critical delay paths of an integrated circuit design is disclosed. The method includes predicting and ranking a set of critical delay paths based on a set of predicted-delay characteristics. Integrated circuits based on the integrated circuit design are tested to determine a set of actual delay measurements for the critical delay paths. The critical delay paths are ranked based on the actual delay measurements, and the results are correlated to the predicted ranking of critical delay paths to produce a confidence measurement that measures the likelihood that the actual critical delay paths of the design have been tested for a given production batch of devices.

Abstract: A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test vectors identifying differences between the original netlist and the modified netlist is identified and used to identify a set of corrections. In one disclosed embodiment, the set of corrections is identified by using an error correction algorithm. Each correction of the set of corrections, when applied to the modified netlist, results in a corrected netlist logically the same as the original netlist. One of the corrections is selected that improves the error characteristic of the original netlist. A final equivalency verification is performed as necessary.