Abstract: A design analysis tool performs path extraction translation and false path identification functions. The design analysis tool is utilized with a conventional automated test pattern generator and timing analysis tools. By checking for four specific criteria, a fast and efficient way to detect whether a circuit path is false or active is accomplished. A final value condition is checked and, if that test is met, a side value propagation condition is checked. Assuming both tests result in the path still being active, the test is terminated. If the side value propagation conditions are not satisfied, then an initial value condition and a slower path condition is checked. The checks are made to determine whether or not conditions exist in the path that makes the path false. The information may be obtained quickly from the timing analysis information and the result of the ATPG tool.

Abstract: A method of generating transition delay fault test patterns creates first and second circuit models of a received circuit model. The second circuit model is a replication of the first circuit model. Each latch of the first circuit model is identified. On a sequential basis until the entire circuit model is transformed, the data input of an identified latch in the first circuit model is disconnected and the data output of the corresponding latch in the second circuit model is disconnected. The driver of the data input of the latch in the first circuit model is connected to what was driven by the data output of the corresponding latch in the second circuit model to form a transformed circuit model. Stuck-at fault testing using conventional ATPG tools is performed on the transformed circuit model and the resulting test vectors are translated to generate transition fault test patterns for the original received circuit model.

Abstract: A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test vectors identifying differences between the original netlist and the modified netlist is identified and used to identify a set of corrections. In one disclosed embodiment, the set of corrections is identified by using an error correction algorithm. Each correction of the set of corrections, when applied to the modified netlist, results in a corrected netlist logically the same as the original netlist. One of the corrections is selected that improves the error characteristic of the original netlist. A final equivalency verification is performed as necessary.

Abstract: A method of generating transition delay fault test patterns creates first and second circuit models of a received circuit model. The second circuit model is a replication of the first circuit model. Each latch of the first circuit model is identified. On a sequential basis until the entire circuit model is transformed, the data input of an identified latch in the first circuit model is disconnected and the data output of the corresponding latch in the second circuit model is disconnected. The driver of the data input of the latch in the first circuit model is connected to what was driven by the data output of the corresponding latch in the second circuit model to form a transformed circuit model. Stuck-at fault testing using conventional ATPG tools is performed on the transformed circuit model and the resulting test vectors are translated to generate transition fault test patterns for the original received circuit model.

Abstract: A design analysis tool performs path extraction translation and false path identification functions. The design analysis tool is utilized with a conventional automated test pattern generator and timing analysis tools. By checking for four specific criteria, a fast and efficient way to detect whether a circuit path is false or active is accomplished. A final value condition is checked and, if that test is met, a side value propagation condition is checked. Assuming both tests result in the path still being active, the test is terminated. If the side value propagation conditions are not satisfied, then an initial value condition and a slower path condition is checked. The checks are made to determine whether or not conditions exist in the path that makes the path false. The information may be obtained quickly from the timing analysis information and the result of the ATPG tool.

Abstract: A method and system for comparing design block views comprising receiving a first design block view, receiving a second design block view, and comparing the first design block view with the second design block view to determine whether the first design block view is logically equivalent to the second design block view, the second design block view contains data representing self-timed circuits or a memory array.