Patents by Inventor Mahadevaiyer Krishnan
Mahadevaiyer Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120083125Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.Type: ApplicationFiled: January 25, 2011Publication date: April 5, 2012Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leslie Charns, John M. Cotte, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lafaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Publication number: 20120040277Abstract: A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.Type: ApplicationFiled: October 21, 2011Publication date: February 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Patent number: 8110321Abstract: A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.Type: GrantFiled: May 16, 2007Date of Patent: February 7, 2012Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Patent number: 8101518Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: GrantFiled: June 11, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
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Publication number: 20120009771Abstract: A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.Type: ApplicationFiled: July 9, 2010Publication date: January 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, JR., John M. Cotte, Dinesh R. Koli, Laura L. Kosbar, Mahadevaiyer Krishnan, Christian Lavoie, Stephen M. Rossnagel, Zhen Zhang
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Patent number: 8039382Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.Type: GrantFiled: August 12, 2009Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan, Jay W. Strane
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Publication number: 20100051474Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.Type: ApplicationFiled: August 27, 2009Publication date: March 4, 2010Inventors: Panayotis C. Andricacos, Caliopi Andricacos, Donald F. Canaperi, Emanuel I. Cooper, John M. Cotte, Hariklia Deligianni, Laertis Economikos, Daniel C. Edelstein, Silvia Franz, Balasubramanian Pranatharthiharan, Mahadevaiyer Krishnan, Andrew P. Mansson, Erick G. Walton, Alan C. West
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Publication number: 20090309228Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.Type: ApplicationFiled: August 12, 2009Publication date: December 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan, Jay W. Strane
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Patent number: 7618891Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.Type: GrantFiled: May 1, 2006Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Sunfei Fang, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan, Jay W. Strane
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Patent number: 7581314Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.Type: GrantFiled: February 21, 2006Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
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Patent number: 7544610Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: GrantFiled: September 7, 2004Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
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Publication number: 20090127711Abstract: A highly reliable copper interconnect structure and method of fabricating the same is provided. The interconnect structure comprises a metal layer buried between an adjacent upper copper layer and an adjacent lower copper layer structure. More specifically, the interconnect structure comprises a recess formed in a dielectric layer; a barrier metal lining sidewalls of the recess; a first copper layer within the recess; a second copper layer within the recess; and a metal layer buried between the first copper layer and the second copper layer. The method comprises forming a recess in an interlayer dielectric; forming a first copper layer, a metal layer over the first copper layer and a second copper layer over the metal layer, all within the recess. The metal layer is sandwiched between the first copper layer and the second copper layer within the recess.Type: ApplicationFiled: November 15, 2007Publication date: May 21, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Daniel C. Edelstein, Mahadevaiyer Krishnan, Takeshi Nogami, David L. Rath
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Publication number: 20080286660Abstract: A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.Type: ApplicationFiled: May 16, 2007Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin S. Petrarca, Donald F. Canaperi, Mahadevaiyer Krishnan, Rebecca D. Mih, Steven Steen, Henry Grabarz, Michael S. Hibbs
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Publication number: 20080274611Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.Type: ApplicationFiled: June 11, 2008Publication date: November 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Michael A. Cobb, Asa Frye, Balasubramanian S. Pranatharthi Haran, Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Andrew P. Mansson, Renee T. Mo, Jay W. Strane, Horatio S. Wildman
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Patent number: 7407605Abstract: An aqueous seeding solution of palladium acetate, acetic acid and chloride.Type: GrantFiled: May 22, 2007Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Darryl D. Restaino, Donald F. Canaperi, Judith M. Rubino, Sean P. E. Smith, Richard O. Henry, James E. Fluegel, Mahadevaiyer Krishnan
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Publication number: 20080156636Abstract: Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening in the insulating layer. Through a chemical mechanical polish, the barrier layer, the impure an impure copper seed layer derived from an electroplated copper bath copper seed layer, and the electroplated copper are planarized to the insulating layer.Type: ApplicationFiled: January 9, 2008Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin S. Petrarca, Mahadevaiyer Krishnan, Michael Lofaro, Kenneth P. Rodbell
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Publication number: 20070254479Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.Type: ApplicationFiled: May 1, 2006Publication date: November 1, 2007Applicant: International Business Machines CorporationInventors: Sunfei Fang, Randolph Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee Mo, Balasubramanian Pranatharthiharan, Jay Strane
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Publication number: 20070215842Abstract: An aqueous seeding solution of palladium acetate, acetic acid and chloride.Type: ApplicationFiled: May 22, 2007Publication date: September 20, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Darryl Restaino, Donald Canaperi, Judith Rubino, Sean Smith, Richard Henry, James Fluegel, Mahadevaiyer Krishnan
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Patent number: 7253106Abstract: A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.Type: GrantFiled: December 22, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Darryl D. Restaino, Donald F. Canaperi, Judith M. Rubino, Sean P. E. Smith, Richard O. Henry, James E. Fluegel, Mahadevaiyer Krishnan
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Patent number: 7202764Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.Type: GrantFiled: July 8, 2003Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund