Abstract: A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.

Abstract: A flip-flop (10) comprises a first latch circuit (18), a second latch circuit (24), and a third latch circuit (26). The first latch circuit (18) is coupled to receive a clock signal and a first power supply voltage. The second latch circuit (24) is coupled to the first latch circuit (18) and receives the clock signal and the first power supply voltage. Preparatory to entering a low power mode, the third latch circuit (26) receives a second power supply voltage and is coupled to the second latch circuit (24) in response to a power down signal. During the low power mode, the first power supply voltage is removed from the first and second latch circuits (18, 24). When returning to a normal operating mode, the first power supply voltage is provided to the first and second latch circuits (18, 24), and the third latch circuit (26) is coupled to the first latch circuit (18) in response to a power restore signal.