Abstract: A semiconductor structure including a nanosheet stack comprising a series of channel nanosheets, a gate structure, first inner spacers, second inner spacers, and a self-aligned backside cap, where the self-aligned backside cap is immediately below the gate structure and between the second inner spacers.

Abstract: Semiconductor devices having a direct backside contact are provided. In one aspect, a semiconductor device includes: at least one FET on a frontside of a wafer, where the wafer includes a semiconductor layer, and where a most backside-facing surface of the semiconductor layer is planar; and a backside contact disposed on the most backside-facing surface of the semiconductor layer, where the backside contact directly contacts source/drain regions of the at least one FET. A local wiring layer can be disposed on a most backside-facing surface of the backside contact. A method of fabricating the present semiconductor devices is also provided.

Abstract: A semiconductor device includes a substrate having a frontside, a backside, and a transistor that includes a gate region, a first source/drain region of a first depth into the substrate, and a second source/drain region of a second depth into the substrate. The semiconductor device further includes a backside contact (BC) region extending from the backside into the substrate and electrically connected to the first source/drain region. The semiconductor device further includes a backside partial diffusion break (BPDB) region that includes a non-conducting material, extending from the backside into the substrate and distinct from the first source/drain region.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a transistor having a metal gate and a dielectric cap on top of the metal gate; and a source/drain contact directly on top of a source/drain region of the transistor, where the source/drain contact has a top portion of a first width in a length direction of the metal gate and a bottom portion of a second width in the length direction of the metal gate with the first width being narrower than the second width. A method of forming the same is also provided.

Abstract: Embodiments relate to backside contact and backside isolation. An aspect includes a semiconductor structure having channel regions connected to a first source/drain region and a second source/drain region and a backside contact disposed under the first source/drain region. An aspect includes a liner vertically extending from a backside of the second source/drain region, the liner protecting the backside of the second source/drain region from contact with the backside contact.

Abstract: A semiconductor IC device includes an isolation bar, nanolayer channels in direct contact with the isolation bar, and a multilayer bottom isolation region in direct contact with the isolation bar. The multilayer bottom isolation region may include a bottom dielectric layer, a middle dielectric layer, and a top dielectric layer. The bottom dielectric layer and the top dielectric layer may be composed of a same first dielectric material. The multilayer bottom isolation region may allow for the formation of a backside contact without an associated backside contact placeholder, which may reduce pitch between transistors and allow for continued semiconductor IC device scaling.

Abstract: Semiconductor devices are provided that include a conductor structure located in a shallow trench isolation structure that is positioned between two field effect transistors of a same conductivity type. The conductor structure is electrically connected to a backside contact structure, and the backside contact structure is electrically connected to at least one well region that straddles a sidewall of the backside contact structure. The area of contact between the backside contact structure and the well region provides a local well tap to the semiconductor device.

Abstract: A semiconductor device includes a shallow trench isolation (STI), a first doped region under the STI, an N-well region connected to the first doped region and the STI on a first side, a P-well region connected to the first doped region and the STI on a second side, a backside contact. A dopant concentration of the first doped region is higher than the dopant concentration of the N-well region and the dopant concentration of the P-well region.

Abstract: A semiconductor device includes a shallow trench isolation (STI), a first well region connected to the insulating region and the STI on a first side, a second well region connected to the insulating region and the STI on a second side, and a backside contact including an upper portion, a lower portion, and a middle portion connecting the upper portion and the lower portion. A shape and a profile of the insulating region is same as a shape and a profile of the middle portion.

Abstract: A semiconductor device including a frontside source/drain contact/via-to-backside power rail (VBPR) structure is provided in which the overlap between the frontside source/drain contact structure of the merged frontside source/drain contact/VBPR structure and the VBPR structure of the merged frontside source/drain contact/VBPR structure is improved. The improved overlap, in turn, provides a structure having low contact resistance.

Abstract: A semiconductor structure with a power rail between at least two front side semiconductor devices and a connector via connecting the power rail to a backside metal layer of a backside power delivery network. The connector via resides within a shallow isolation trench. The connector via has a top surface that is below the top surface of the shallow isolation trench. The connector via provides a direct connection between the power rail connecting to at least one of the front side semiconductor devices and the backside power delivery network.

Abstract: A semiconductor device includes a first metal line, and a second metal line adjacent and coplanar to the first metal line. The first metal line and the second metal line have a common patterning level, and the first metal line and the second metal line are separated by a cut region parallel to a length of the first metal line and the second metal line.

Abstract: A semiconductor structure is provided. In one embodiment, the semiconductor structure includes a first inner spacer and a second inner spacer disposed on a silicon layer, a third inner spacer disposed on the first inner spacer, a fourth inner spacer disposed on the second inner spacer, a gate region disposed on the silicon layer, and a source/drain region disposed on a backside source/drain contact, where an upper surface of the backside source/drain contact is disposed above a bottom surface of the first inner spacer or the second inner spacer, and where the upper surface of the backside source/drain contact is disposed below an upper surface of the third inner spacer or the fourth inner spacer.

Abstract: Embodiments of the present disclosure are directed to processing methods and resulting structures for providing robust backside contacts. In a non-limiting embodiment, a backside contact is electrically coupled to a first source or drain (S/D) region and a frontside contact electrically coupled to a second S/D region. A backside contact dielectric liner wraps around the backside contact. The backside contact dielectric liner includes an L-shaped spacer having direct contact with a shoulder surface and a sidewall surface of the backside contact.

Abstract: A semiconductor device includes a backside source/drain contact and a placeholder disposed between a first gate cut portion and a second gate cut portion, where the backside source/drain contact contacts a frontside inter-layer dielectric layer disposed between a first gate structure associated with the first gate cut portion and a second gate structure associated with the second gate cut portion.

Abstract: A semiconductor structure is presented including a power rail having a non-rectangular shape and a middle-of-line (MOL) contact layer electrically connected to the power rail by a metal wiring layer. The non-rectangular shape of the power rail defines at least one notch. Alternatively, the non-rectangular shape of the power rail defines at least one extension. The power rail can be a via rail or a VARAIL.

Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.

Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.

Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.

Abstract: Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.