Patents by Inventor Mahender Kumar
Mahender Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10770388Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.Type: GrantFiled: June 15, 2018Date of Patent: September 8, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo, Mahender Kumar, Guillaume Bouche
-
Patent number: 10566328Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.Type: GrantFiled: February 26, 2018Date of Patent: February 18, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Bala Haran, Christopher Sheraw, Mahender Kumar
-
Publication number: 20190385946Abstract: A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Applicant: International Business Machines CorporationInventors: Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo, Mahender Kumar, Guillaume Bouche
-
Patent number: 10461186Abstract: Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.Type: GrantFiled: May 31, 2018Date of Patent: October 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: John H. Zhang, Ruilong Xie, Mahender Kumar
-
Publication number: 20190267371Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.Type: ApplicationFiled: February 26, 2018Publication date: August 29, 2019Inventors: Bala Haran, Christopher Sheraw, Mahender Kumar
-
Publication number: 20190139830Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.Type: ApplicationFiled: November 3, 2017Publication date: May 9, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Ruilong XIE, Minoli K. PATHIRANE, Chanro PARK, Guillaume BOUCHE, Nigel CAVE, Mahender KUMAR, Min Gyu SUNG, Huang LIU, Hui ZANG
-
Patent number: 9812324Abstract: A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.Type: GrantFiled: January 13, 2017Date of Patent: November 7, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Lei Zhuang, Lars Liebmann, Stuart A. Sieg, Fee Li Lie, Mahender Kumar, Shreesh Narasimha, Ahmed Hassan, Guillaume Bouche, Xintuo Dai
-
Patent number: 9780002Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.Type: GrantFiled: June 6, 2016Date of Patent: October 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xintuo Dai, Brian Greene, Mahender Kumar, Daniel J. Dechene, Daniel Jaeger
-
Patent number: 8610217Abstract: Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region).Type: GrantFiled: December 14, 2010Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Robert J. Gauthier, Jr., Mahender Kumar, Junjun Li, Dustin K. Slisher
-
Publication number: 20120146150Abstract: Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region).Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Robert J. Gauthier, JR., Mahender Kumar, Junjun Li, Dustin K. Slisher
-
Patent number: 8188574Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.Type: GrantFiled: February 12, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Matthew S. Angyal, Mahender Kumar, Effendi Leobandung, Jay W. Strane
-
Patent number: 8053838Abstract: A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.Type: GrantFiled: June 26, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, Byeong Yeol Kim, Mahender Kumar, Huilong Zhu
-
Patent number: 7943474Abstract: A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.Type: GrantFiled: February 24, 2009Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Keith Kwong Hon Wong, Mahender Kumar
-
Patent number: 7911024Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: GrantFiled: February 17, 2010Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
-
Patent number: 7790553Abstract: Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.Type: GrantFiled: July 10, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Xiaomeng Chen, Mahender Kumar, Brian J. Greene, Bachir Dirahoui, Jay W. Strane, Gregory G. Freeman
-
Patent number: 7790541Abstract: A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.Type: GrantFiled: December 4, 2007Date of Patent: September 7, 2010Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (AMD)Inventors: Bruce B. Doris, Mahender Kumar, Werner A. Rausch, Robin Van Den Nieuwenhuizen
-
Publication number: 20100213571Abstract: A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.Type: ApplicationFiled: February 24, 2009Publication date: August 26, 2010Applicant: International Business Machines CorporationInventors: Thomas W. Dyer, Keith Kwong Hon Wong, Mahender Kumar
-
Publication number: 20100207683Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: ApplicationFiled: February 17, 2010Publication date: August 19, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt
-
Publication number: 20100200958Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.Type: ApplicationFiled: February 12, 2010Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Angyal, Mahender Kumar, Effendi Leobandung, Jay W. Strane
-
Patent number: 7763518Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.Type: GrantFiled: April 8, 2008Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Mahender Kumar, Qiqing Ouyang, Paul A. Papworth, Christopher D. Sheraw, Michael D. Steigerwalt