Abstract: A semiconductor device includes a gate region, an active region surrounded by the gate region, at least one source/drain region, and a backside contact below the at least one source/drain region and having a first portion with a first height. A length of the first portion along the active region is smaller than a length of the active region.

Abstract: A semiconductor device includes a vertical bipolar junction device, having a collector, a base over the collector, an emitter over the base, one or more source/drain region/dummy and dummy gate alternatively and laterally extended over the emitter, and a contact over source/drain regions of the one or more source/drain region/dummy gate.

Abstract: A nanosheet semiconductor structure including a backside contact structure beneath a first source drain region, and a bottom inner spacer directly beneath a second source drain region adjacent to the backside contact structure.

Abstract: A semiconductor integrated circuit (IC) devices are described. The IC devices include a confined backside contact that includes and upper portion and a lower portion in direct contact with the upper portion. The confined backside contact may be formed by processes which may result in the formation of the upper portion and lower portion. The processes may ease possible masking, photolithography, feature placement and/or alignment challenges in the formation of backside contacts and may reduce backside contact shorting failures, thereby increasing yield of the IC devices.

Abstract: An integrated circuit includes a first cell of a first cell height having a first feature and a second cell of a second cell height having a second feature corresponding to the first feature. The first cell height is greater than the second cell height. A transition region borders the first cell and the second cell. The transition region includes a change in dimension between the first feature and the second feature.

Abstract: A semiconductor structure including a nanosheet stack comprising a series of channel nanosheets, dielectric nanosheet layers arranged directly beneath the series of channel nanosheets, and semiconductor layers between and physically separating the dielectric nanosheet layers from one another.

Abstract: A semiconductor device includes a base, an emitter, a collector between the base and the emitter, a well region below the base, the emitter and the collector, and an isolating layer extended horizontally and at least partially isolating the well region from the collector and the emitter.

Abstract: A semiconductor device, comprising a source/drain epitaxy. A first dielectric cap is under the source/drain epitaxy on a backside of the semiconductor device. The semiconductor device includes a gate and a second dielectric cap formed under the gate. A spacer separates the first dielectric cap and the source/drain epitaxy from the second dielectric cap and the gate.

Abstract: A semiconductor structure including a nanosheet stack comprising a series of channel nanosheets, a gate structure, first inner spacers, second inner spacers, and a self-aligned backside cap, where the self-aligned backside cap is immediately below the gate structure and between the second inner spacers.

Abstract: Semiconductor devices having a direct backside contact are provided. In one aspect, a semiconductor device includes: at least one FET on a frontside of a wafer, where the wafer includes a semiconductor layer, and where a most backside-facing surface of the semiconductor layer is planar; and a backside contact disposed on the most backside-facing surface of the semiconductor layer, where the backside contact directly contacts source/drain regions of the at least one FET. A local wiring layer can be disposed on a most backside-facing surface of the backside contact. A method of fabricating the present semiconductor devices is also provided.

Abstract: A semiconductor device includes a substrate having a frontside, a backside, and a transistor that includes a gate region, a first source/drain region of a first depth into the substrate, and a second source/drain region of a second depth into the substrate. The semiconductor device further includes a backside contact (BC) region extending from the backside into the substrate and electrically connected to the first source/drain region. The semiconductor device further includes a backside partial diffusion break (BPDB) region that includes a non-conducting material, extending from the backside into the substrate and distinct from the first source/drain region.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a transistor having a metal gate and a dielectric cap on top of the metal gate; and a source/drain contact directly on top of a source/drain region of the transistor, where the source/drain contact has a top portion of a first width in a length direction of the metal gate and a bottom portion of a second width in the length direction of the metal gate with the first width being narrower than the second width. A method of forming the same is also provided.

Abstract: Embodiments relate to backside contact and backside isolation. An aspect includes a semiconductor structure having channel regions connected to a first source/drain region and a second source/drain region and a backside contact disposed under the first source/drain region. An aspect includes a liner vertically extending from a backside of the second source/drain region, the liner protecting the backside of the second source/drain region from contact with the backside contact.

Abstract: A semiconductor IC device includes an isolation bar, nanolayer channels in direct contact with the isolation bar, and a multilayer bottom isolation region in direct contact with the isolation bar. The multilayer bottom isolation region may include a bottom dielectric layer, a middle dielectric layer, and a top dielectric layer. The bottom dielectric layer and the top dielectric layer may be composed of a same first dielectric material. The multilayer bottom isolation region may allow for the formation of a backside contact without an associated backside contact placeholder, which may reduce pitch between transistors and allow for continued semiconductor IC device scaling.

Abstract: Semiconductor devices are provided that include a conductor structure located in a shallow trench isolation structure that is positioned between two field effect transistors of a same conductivity type. The conductor structure is electrically connected to a backside contact structure, and the backside contact structure is electrically connected to at least one well region that straddles a sidewall of the backside contact structure. The area of contact between the backside contact structure and the well region provides a local well tap to the semiconductor device.

Abstract: A semiconductor device includes a shallow trench isolation (STI), a first doped region under the STI, an N-well region connected to the first doped region and the STI on a first side, a P-well region connected to the first doped region and the STI on a second side, a backside contact. A dopant concentration of the first doped region is higher than the dopant concentration of the N-well region and the dopant concentration of the P-well region.

Abstract: A semiconductor device includes a shallow trench isolation (STI), a first well region connected to the insulating region and the STI on a first side, a second well region connected to the insulating region and the STI on a second side, and a backside contact including an upper portion, a lower portion, and a middle portion connecting the upper portion and the lower portion. A shape and a profile of the insulating region is same as a shape and a profile of the middle portion.

Abstract: A semiconductor device including a frontside source/drain contact/via-to-backside power rail (VBPR) structure is provided in which the overlap between the frontside source/drain contact structure of the merged frontside source/drain contact/VBPR structure and the VBPR structure of the merged frontside source/drain contact/VBPR structure is improved. The improved overlap, in turn, provides a structure having low contact resistance.

Abstract: A semiconductor structure with a power rail between at least two front side semiconductor devices and a connector via connecting the power rail to a backside metal layer of a backside power delivery network. The connector via resides within a shallow isolation trench. The connector via has a top surface that is below the top surface of the shallow isolation trench. The connector via provides a direct connection between the power rail connecting to at least one of the front side semiconductor devices and the backside power delivery network.

Abstract: A semiconductor device includes a first metal line, and a second metal line adjacent and coplanar to the first metal line. The first metal line and the second metal line have a common patterning level, and the first metal line and the second metal line are separated by a cut region parallel to a length of the first metal line and the second metal line.