Patents by Inventor Mahesh BHATKAR
Mahesh BHATKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10566384Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: GrantFiled: October 30, 2018Date of Patent: February 18, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Neha Nayyar, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wenjun Liu, Juan Boon Tan
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Patent number: 10553488Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: GrantFiled: September 21, 2017Date of Patent: February 4, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
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Patent number: 10483461Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.Type: GrantFiled: April 19, 2018Date of Patent: November 19, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Bharat Bhushan, Mahesh Bhatkar, Juan Boon Tan
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Publication number: 20190326509Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.Type: ApplicationFiled: April 19, 2018Publication date: October 24, 2019Inventors: Wanbing YI, Curtis Chun-I HSIEH, Yi JIANG, Bharat BHUSHAN, Mahesh BHATKAR, Juan Boon TAN
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Patent number: 10381403Abstract: A method for forming a MRAM device free of seal ring peeling defect, and the resulting device, are provided. Embodiments include forming magnetic tunnel junction (MTJ) over a metallization layer in a seal ring region of an MRAM device; forming a metal filled via connecting the MTJ and the metallization layer; forming a tunnel junction via over the MTJ; and forming a top electrode over the tunnel junction via.Type: GrantFiled: June 21, 2018Date of Patent: August 13, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yi Jiang, Bharat Bhushan, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wanbing Yi, Juan Boon Tan
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Publication number: 20190074434Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: ApplicationFiled: October 30, 2018Publication date: March 7, 2019Inventors: Wanbing YI, Neha NAYYAR, Curtis Chun-I HSIEH, Mahesh BHATKAR, Wenjun LIU, Juan Boon TAN
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Patent number: 10217794Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.Type: GrantFiled: May 30, 2018Date of Patent: February 26, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Juan Boon Tan, Mahesh Bhatkar, Bhushan Bharat, Wanbing Yi
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Patent number: 10158066Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: GrantFiled: June 7, 2017Date of Patent: December 18, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Neha Nayyar, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wenjun Liu, Juan Boon Tan
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Publication number: 20180358546Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: ApplicationFiled: June 7, 2017Publication date: December 13, 2018Inventors: Wanbing YI, Neha NAYYAR, Curtis Chun-I HSIEH, Mahesh BHATKAR, Wenjun LIU, Juan Boon TAN
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Publication number: 20180342556Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.Type: ApplicationFiled: May 30, 2018Publication date: November 29, 2018Inventors: Juan Boon Tan, Mahesh Bhatkar, Bhushan Bharat, Wanbing Yi
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Patent number: 10121755Abstract: A seal ring structure is disclosed for integrated circuit (IC) packaging. The seal ring includes an inner moisture barrier ring and an outer crack stop ring. Line structures of both the inner and outer rings include chamfered corners. The chamfers of a chamfered corner are devoid of acute angles. No metal line structure for the inner ring is provided at the pad level. The seal ring as described improves the reliability and strength of the structure and hence the seal ring can sustain high stress at the corners of the die during dicing.Type: GrantFiled: September 24, 2017Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Mahesh Bhatkar, Juan Boon Tan, Wanbing Yi
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Patent number: 10062733Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a memory cell with a memory cell upper surface. A capping layer is formed overlying the memory cell, and a portion of the capping layer is removed to expose the memory cell upper surface. A memory cell etch stop is formed overlying the memory cell upper surface after the portion of the capping layer is removed to expose the memory cell upper surface. The memory cell etch stop is removed from overlying the memory cell upper surface, and an interconnect is formed in electrical communication with the memory cell.Type: GrantFiled: May 31, 2017Date of Patent: August 28, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Mahesh Bhatkar, Hui Liu, Chin Chuan Neo
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Patent number: 9917027Abstract: A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.Type: GrantFiled: December 30, 2015Date of Patent: March 13, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Mahesh Bhatkar, Chin Chuan Neo, Juan Boon Tan
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Publication number: 20180012800Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: ApplicationFiled: September 21, 2017Publication date: January 11, 2018Inventors: Shunqiang GONG, Juan Boon TAN, Shijie WANG, Mahesh BHATKAR, Daxiang WANG
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Patent number: 9773702Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: GrantFiled: December 28, 2015Date of Patent: September 26, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
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Patent number: 9728474Abstract: A semiconductor chip includes an active area including a plurality of integrated circuit structures, a seal ring enclosing the active area, a corner area of the semiconductor chip that is outside of the seal ring, and an electronic test structure disposed within the corner area. Semiconductor wafers including the above-noted semiconductor chips, as well as methods for fabricating semiconductor wafers including the above-noted semiconductor chips, are also disclosed.Type: GrantFiled: September 28, 2016Date of Patent: August 8, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Juan Boon Tan, Mahesh Bhatkar, Danny Pak-Chum Shum
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Publication number: 20170194229Abstract: A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventors: Wanbing Yi, Mahesh Bhatkar, Chin Chuan Neo, Juan Boon Tan
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Patent number: 9613897Abstract: Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.Type: GrantFiled: November 11, 2014Date of Patent: April 4, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Mahesh Bhatkar, Lulu Peng, Wanbing Yi, Juan Boon Tan, Luke England
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Publication number: 20160190041Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: ApplicationFiled: December 28, 2015Publication date: June 30, 2016Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
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Publication number: 20160133565Abstract: Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.Type: ApplicationFiled: November 11, 2014Publication date: May 12, 2016Inventors: Mahesh Bhatkar, Lulu Peng, Wanbing Yi, Juan Boon Tan, Luke England