Patents by Inventor Mahesh K. Kumashikar

Mahesh K. Kumashikar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240346224
    Abstract: Systems or methods of the present disclosure may provide a multi-chip package with two or more integrated circuit devices that each include hybrid bumps. The hybrid bumps may include bumps of different sizes to facilitate different types of communication. For example, the hybrid bumps may include a first bump with fine pitch for die-to-die communication and/or a second bump with a large pitch for off-package communication. The multi-chip package may include a bridge to facilitate signal transfer between the integrated circuit device with the hybrid bumps and other components within the multi-chip package. Additionally or alternatively, the multi-chip package may include an interconnect to facilitate signal transfer between two integrated circuit devices. The interconnect may include fine pitch bumps, which may be translated by an interposer to a pitch size of the bridge. As such, the interconnect may facilitate die-to-die communication and/or off-package communication.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Mahesh K. Kumashikar, Atul Maheshwari, MD Altaf Hossain, Ankireddy Nalamalpu, Krishna Bharath Kolluru
  • Publication number: 20240348253
    Abstract: Systems or methods of the present disclosure may provide an integrated circuit device that implements one region definition, which may decrease design complexity, decrease software complexity, and increase ease of use. For example, the integrated circuit device may include programmable logic that implements one region definition. The region definition may include circuitry that may implement three-dimensional (3D) input/output circuitry, 2.5D input/output circuitry, circuitry for intra-die communication, circuitry for inter-package communication, or any combination thereof. By implementing one region definition on the integrated circuit device, time spent defining each programmable logic region may be reduced or eliminated, thereby reducing design complexity software complexity associated with the integrated circuit device.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Atul Maheshwari, Mahesh K. Kumashikar, MD Altaf Hossain, Ankireddy Nalamalpu, Krishna Bharath Kolluru, Jeffrey Christopher Chromczak
  • Patent number: 11899615
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • Publication number: 20230341463
    Abstract: Systems and methods are provided to enable efficient testing of an integrated circuit package. Such a system may include an integrated circuit package and a testing device to test a first portion of socket pins of the integrated circuit package corresponding to a first portion of a die area using a socket during a first pass, and test a second portion of socket pins of the integrated circuit package corresponding to a second portion of the die area using the socket during a second pass.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Inventors: Kalyana Ravindra Kantipudi, Mahesh K. Kumashikar, MD Altaf Hossain, Ankireddy Nalamalpu
  • Publication number: 20230169032
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Application
    Filed: January 27, 2023
    Publication date: June 1, 2023
    Inventors: NEVINE NASSIF, YEN-CHENG LIU, KRISHNAKANTH V. SISTLA, GERALD PASDAST, SIVA SOUMYA EACHEMPATI, TEJPAL SINGH, ANKUSH VARMA, MAHESH K. KUMASHIKAR, SRIKANTH NIMMAGADDA, CARLETON L. MOLNAR, VEDARAMAN GEETHA, JEFFREY D. CHAMBERLAIN, WILLIAM R. HALLECK, GEORGE Z. CHRYSOS, JOHN R. AYERS, DHEERAJ R. SUBBAREDDY
  • Patent number: 11586579
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z. Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • Publication number: 20230042718
    Abstract: Systems or methods of the present disclosure may provide an integrated circuit system. The integrated circuit system may implement a circuit design. Design software models a circuit design for the integrated circuit system and the circuit design is agnostic of physical layer circuitry of the integrated circuit system. The design software may generate configuration data based on the circuit design and transfer the configuration data to the integrated circuit system to cause programmable logic of the integrated circuit system to implement the circuit design.
    Type: Application
    Filed: September 29, 2022
    Publication date: February 9, 2023
    Inventors: Ankireddy Nalamalpu, Mahesh K. Kumashikar, Atul Maheshwari, Lai Guan Tang
  • Publication number: 20230028475
    Abstract: A system includes a first die having a first side with first die-to-die circuitry and first input output circuitry. The system also includes a second die comprising a second side with second die-to-die circuitry and second input output circuitry. The first and second sides are adjacent to each other in the electronic package device. The system also includes a semiconductor interconnect including multiple connections to interconnect the first and second die-to-die circuitries. The semiconductor interconnect also includes multiple through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Inventors: Ankireddy Nalamalpu, Mahesh K. Kumashikar, Atul Maheshwari, Lai Guan Tang
  • Publication number: 20230024515
    Abstract: A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Inventors: Atul Maheshwari, Mahesh K. Kumashikar, Ankireddy Nalamalpu, MD Altaf Hossain, Mahesh A. Iyer
  • Publication number: 20230024662
    Abstract: A die includes one or more power delivery layers to deliver power within the die. Additionally, the die also includes one or more transistor layers to at least partially implement a programmable fabric for the die. Furthermore, the die further includes one or more signal routing layers to transmit signals for use by the programmable fabric. Moreover, the one or more transistor layers physically separate the one or more power delivery layers from the one or more signal routing layers.
    Type: Application
    Filed: September 30, 2022
    Publication date: January 26, 2023
    Inventors: Ankireddy Nalamalpu, Mahesh K. Kumashikar, Atul Maheshwari, Lai Guan Tang
  • Publication number: 20220337250
    Abstract: This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Mahesh K. Kumashikar, Ankireddy Nalamalpu, Atul Maheshwari, Lai Guan Tang
  • Publication number: 20220336415
    Abstract: Systems and methods are provided for a modular die-to-die interconnect for integrated circuits in a three-dimensional arrangement. An integrated circuit system may include a first chiplet that includes a grid-based interconnect field and a second chiplet that includes a complementary grid-based interconnect field. A number of interconnects of the complementary grid-based interconnect field of the second chiplet are connected to a corresponding number of interconnects of the grid-based interconnect field of the first chiplet.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Mahesh K. Kumashikar, Atul Maheshwari
  • Publication number: 20220337251
    Abstract: Systems and methods are provided for system circuitry disaggregation into an integrated circuit system with multiple chiplets having disaggregated components. A system may include a first programmable logic fabric die that includes programmable logic circuitry and a number of supporting chiplets that include disaggregated field programmable gate array (FPGA) circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Ankireddy Nalamalpu, Mahesh K. Kumashikar, Atul Maheshwari, Lai Guan Tang
  • Publication number: 20220294455
    Abstract: Systems or methods of the present disclosure may provide a programmable logic device including one or more power monitors and one or more thermal sensors. The programmable logic device may include control circuitry that may receive power data and thermal data for multiple die of the programmable logic device, and may implement one or more response based on the thermal and power data.
    Type: Application
    Filed: April 1, 2022
    Publication date: September 15, 2022
    Inventors: Mahesh K. Kumashikar, Ankireddy Nalamalpu, Atul Maheshwari, Lai Guan Tang
  • Publication number: 20220229941
    Abstract: Systems or methods of the present disclosure may provide a semiconductor device including a die of a multi-die package including encryption circuitry to receive data and to encrypt the data to generate encrypted data; and a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 21, 2022
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Mahesh K. Kumashikar, Atul Maheshwari
  • Publication number: 20220224342
    Abstract: A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: Atul Maheshwari, Ankireddy Nalamalpu, Mahesh K. Kumashikar, Lai Guan Tang
  • Publication number: 20220113756
    Abstract: Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Atul Maheshwari, Ankireddy Nalamalpu, Mahesh A. Iyer, Mahesh K. Kumashikar
  • Publication number: 20220116045
    Abstract: An integrated circuit device that includes programmable logic circuitry that includes a plurality of regions each configured to operate at different voltage levels. The regions may be separated by level shifters that enable communication between the different voltage level regions. The integrated circuitry may also include software that performs voltage aware placement and routing for a user register-transfer level design, and may direct logic to regions according to voltages defined for the regions.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Mahesh K. Kumashikar, Ankireddy Nalamalpu, MD Altaf Hossain, Atul Maheshwari, Yuet Li, Mahesh A. Iyer
  • Publication number: 20220116038
    Abstract: Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Mahesh K. Kumashikar, MD Altaf Hossain, Yuet Li, Atul Maheshwari, Ankireddy Nalamalpu
  • Publication number: 20220113350
    Abstract: Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Dheeraj Subbareddy, Arun Jangity, Ramya Yeluri, Mahesh K. Kumashikar, Atul Maheshwari, Ankireddy Nalamalpu