Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Abstract: Systems and methods are provided to enable efficient testing of an integrated circuit package. Such a system may include an integrated circuit package and a testing device to test a first portion of socket pins of the integrated circuit package corresponding to a first portion of a die area using a socket during a first pass, and test a second portion of socket pins of the integrated circuit package corresponding to a second portion of the die area using the socket during a second pass.

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Abstract: Systems or methods of the present disclosure may provide an integrated circuit system. The integrated circuit system may implement a circuit design. Design software models a circuit design for the integrated circuit system and the circuit design is agnostic of physical layer circuitry of the integrated circuit system. The design software may generate configuration data based on the circuit design and transfer the configuration data to the integrated circuit system to cause programmable logic of the integrated circuit system to implement the circuit design.

Abstract: A die includes one or more power delivery layers to deliver power within the die. Additionally, the die also includes one or more transistor layers to at least partially implement a programmable fabric for the die. Furthermore, the die further includes one or more signal routing layers to transmit signals for use by the programmable fabric. Moreover, the one or more transistor layers physically separate the one or more power delivery layers from the one or more signal routing layers.

Abstract: A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.

Abstract: A system includes a first die having a first side with first die-to-die circuitry and first input output circuitry. The system also includes a second die comprising a second side with second die-to-die circuitry and second input output circuitry. The first and second sides are adjacent to each other in the electronic package device. The system also includes a semiconductor interconnect including multiple connections to interconnect the first and second die-to-die circuitries. The semiconductor interconnect also includes multiple through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge.

Abstract: This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.

Abstract: Systems and methods are provided for system circuitry disaggregation into an integrated circuit system with multiple chiplets having disaggregated components. A system may include a first programmable logic fabric die that includes programmable logic circuitry and a number of supporting chiplets that include disaggregated field programmable gate array (FPGA) circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.

Abstract: Systems and methods are provided for a modular die-to-die interconnect for integrated circuits in a three-dimensional arrangement. An integrated circuit system may include a first chiplet that includes a grid-based interconnect field and a second chiplet that includes a complementary grid-based interconnect field. A number of interconnects of the complementary grid-based interconnect field of the second chiplet are connected to a corresponding number of interconnects of the grid-based interconnect field of the first chiplet.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including one or more power monitors and one or more thermal sensors. The programmable logic device may include control circuitry that may receive power data and thermal data for multiple die of the programmable logic device, and may implement one or more response based on the thermal and power data.

Abstract: Systems or methods of the present disclosure may provide a semiconductor device including a die of a multi-die package including encryption circuitry to receive data and to encrypt the data to generate encrypted data; and a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die.

Abstract: A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.

Abstract: Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.

Abstract: Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Abstract: Systems or methods of the present disclosure may provide for operating a programmable fabric including multiple programmable elements organized into a number of power domains that utilize a common voltage within the respective power domains. A current sensor senses a current of the programmable fabric. When the sensed current has crossed a threshold, the programmable fabric changes the number of power domains.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.

Abstract: Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.