Abstract: The present invention is directed to a method and system for detecting component level changes in a storage area network during power off state is provided. Storage profile changes may be utilized for monitoring components during a power cycle period of a storage array system coupled to a SAN. During the power on state of the storage array system, a storage profile (an on-power-storage profile) is collected and time stamped after predefined set of trigger points. Another storage profile (an off-power-storage profile) of the same storage array system may be collected immediately after a power cycle. The two versions of the storage profiles are compared immediately after the off-power-storage profile is created to determine whether the predetermined condition happened. A delta file may be generated after the comparison of the two versions of storage profiles. Each detected conditions may be logged in a log file of the storage array system.

Abstract: An apparatus comprising a storage array, a primary controller, a secondary controller and a solid state device. The storage array may be configured to be accessed by a plurality of controllers. A first of the plurality of the controllers may be configured as the primary controller configured to read and write to and from the storage array during a normal condition. A second of the plurality of the controllers may be configured as the secondary controller configured to read and write to and from the storage array during a fault condition. The solid state device may be configured to (i) store data and (ii) be accessed by the storage array and the secondary controller.

Abstract: A method comprising the steps of (A) generating a call for a first operating system at a host, (B) sending the call for the first operating system from the host to a storage array over a network, (C) generating a response to the call for the first operating system from the host, (D) sending the response from the storage array to the host over the network and (E) capturing and storing the response in a device.

Abstract: An apparatus comprising a storage array, a controller, a cache storage area and a backup storage area. The storage array may include a plurality of storage devices. The controller may be configured to send one or more commands configured to control reading and writing data to and from the storage array. The commands may include volume configuration information used by each of the plurality of storage devices. The cache storage area may be within the controller and may be configured to store a copy of the commands. The backup storage area may be configured to store the copy of the commands during a power failure.

Abstract: A method for capturing data comprising the steps of (A) handling a call for a first operating system at a storage library, (B) routing the call from the storage library to a controller firmware, (C) sending a response to the call from the controller firmware to the storage library, and (D) storing the response in a data store box for later use by the storage library.

Abstract: A system comprising a host, a solid state device, and an abstract layer. The host may be configured to generate a plurality of input/output (IO) requests. The solid state device may comprise a write cache region and a read cache region. The read cache region may be a mirror of the write cache region. The abstract layer may be configured to (i) receive the plurality of IO requests, (ii) process the IO requests, and (iii) map the plurality of IO requests to the write cache region and the read cache region.

Abstract: An apparatus and method to dynamically allocate cache in a SAN controller between a first fixed cache comprising traditional RAID cache comprised of RAM and a second, scalable RAID cache comprising of SSDs (Solid State Devices). The method is dynamic and switches between the first and second cache depending on IO demand.

Abstract: A method for controlling and emulating the functional and logical behaviors of an array of storage devices is established by loading a software module to an array controller board. The software module is integrated into the array controller subsystem manager by providing the necessary parameters required to insert the device and can control the inbound and outbound activities (commands, data, and status packages) regardless of the type, interface, and protocol of the disk/tape device. This aspect of the method allows the user to control the drive state transition and inject errors on the inbound and outbound drive traffics. Also, the method of this invention allows the drive module to recover in case of an array controller failure and to be removed from a list of devices like a regular drive.

Abstract: A method for controlling and emulating the functional and logical behaviors of an array of storage devices is established by loading a software module to an array controller board. The software module is integrated into the array controller subsystem manager by providing the necessary parameters required to insert the device and can control the inbound and outbound activities (commands, data, and status packages) regardless of the type, interface, and protocol of the disk/tape device. This aspect of the method allows the user to control the drive state transition and inject errors on the inbound and outbound drive traffics. Also, the method of this invention allows the drive module to recover in case of an array controller failure and to be removed from a list of devices like a regular drive.

Abstract: A method for isolating SAN Fibre Channel faults in both laboratory and customer site environments, thereby reducing or eliminating uncertainty typically involved in isolating faulty components and decreasing fault isolation time is disclosed. The method provides multiple levels of analysis including providing diagnostic information for a component within the SAN Fibre Channel environment, the diagnostic information being suitable for indicating a fault of the component; analyzing the diagnostic information for determining a cause of a fault indicated by the diagnostic information; and furnishing a possible cause of the fault indicated by the diagnostic information based on analysis of the provided diagnostic information. In exemplary embodiments, the method may be implemented by a Fibre Channel fault isolator coupled to the SAN.

Abstract: A logic analyzer or a bus analyzer may be used to capture data from a source computer system to diagnose a problem arising in the source computer system. In many cases the problem can be traced to a particular hardware/software subsystem. Quite often, a customer of the manufacturer of the hardware/software subsystem maintains the source computer system. In the manufacturer's facilities is a reference system operated by a technician or engineer responsible to test and support the hardware/software subsystem. The source computer system and the reference system thus may involve different hardware and software configurations and possibly even different operating systems. The present invention provides a system and a method to allow data captured in a source computer system to be replayed in the remote reference system so as to recreate a captured event or analyze performance.

Abstract: A system and method for isolating faulty connections in a storage area network, by identifying faulty passive connectivity components in both laboratory and customer site environments. Being independent of the operating system, protocol and components of the Storage Area Network (SAN) the method is passive with respect to live data transmissions within the SAN and is capable of testing the access and reach ability to all the active devices without impacting or changing the configuration and the setup parameters. The method enables the execution of a plurality of procedures including a host/client procedure, a host_switch procedure and an array controller procedure. The system may be a faulty connection and loss of access detection mechanism connected to the SAN or integrated within a SAN component device.

Abstract: A testing system includes a controller, a device driver for the controller, and a processor. The controller is operable to control a device coupled thereto. The device driver is operable to provide a generic interface for data transfers to and from the controller. The processor is coupled to coupled to the controller and is operable to execute a test script having a plurality of script commands. Moreover, the processor is operable to transfer test data to the controller via the generic interface of the device driver in response to executing a first script command of the plurality of script commands. The processor is also operable to receive status information from the controller via the controller generic interface.

Abstract: A logic analyzer or a bus analyzer may be used to capture data from a source computer system to diagnose a problem arising in the source computer system. In many cases the problem can be traced to a particular hardware/software subsystem. Quite often, a customer of the manufacturer of the hardware/software subsystem maintains the source computer system. In the manufacturer's facilities is a reference system operated by a technician or engineer responsible to test and support the hardware/software subsystem. The source computer system and the reference system thus may involve different hardware and software configurations and possibly even different operating systems. The present invention provides a system and a method to allow data captured in a source computer system to be replayed in the remote reference system so as to recreate a captured event or analyze performance.

Abstract: A logic analyzer or a bus analyzer may be used to capture data from a source computer system to diagnose a problem arising in the source computer system. In many cases the problem can be traced to a particular hardware/software subsystem. Quite often, a customer of the manufacturer of the hardware/software subsystem maintains the source computer system. In the manufacturer's facilities is a reference system operated by a technician or engineer responsible to test and support the hardware/software subsystem. The source computer system and the reference system thus may involve different hardware and software configurations and possibly even different operating systems. The present invention provides a system and a method to allow data captured in a source computer system to be replayed in the remote reference system so as to recreate a captured event or analyze performance.

Abstract: A scripting tool for executing a script command having at least one parameter includes a display device, a processor, and a memory. The memory has stored therein instructions which when executed by the processor cause the processor to generate a user input control for a parameter of the script command based upon a definition file, and display the user input control upon the display device. The instructions of the memory when executed by the processor further cause the processor to receive user input via the user input control, and generate a parameter value based upon the user input. Moreover, the instructions when executed by the processor cause the processor to set the parameter of the script command equal to the parameter value, and execute the script command based upon the parameter.

Abstract: An interrupt signal indicating the existence of a bus configuration error within a disk array system is generated by monitoring the enable signals controlling bus drivers included in the array system. The array configuration error detector includes bus configuration error detection logic for each multiple-source bus within the array. Each bus configuration error detector is connected to receive all enable signals for the bus drivers associated with one bus and decode the received enable signals to generate an error signal when more than one of the received enable signals is active. The error signals generated for each of the multiple-source busses are provided to an adder and combined to form the configuration error interrupt signal for the array.

Abstract: A simple method and circuit for qualifying and combining individual request signals received from a plurality of disk drives within a disk array to generate a single, synchronized request signal for the disk array. The circuit includes an activity register for storing a bit pattern which identifies those disk drives which are in use within the array. Each bit position within the activity corresponds to a different disk drive within the disk array. A logic one stored in a bit position identifies the disk drive corresponding to the bit position as being active while a logic zero stored in a bit position identifies the disk drive corresponding to the bit position as being inactive.

Abstract: A disk array controller including a data path architecture which can be configured to perform data transfer operations between a host system and a plurality of disk drives configured as a RAID level 1, 3, 4 of 5 disk array. The data path architecture includes a plurality of array channels for coupling selected disk drives with a host system bus and circuitry for generating parity information during write operations. Each array channel includes a data bus connected through bus drivers to the host bus, its associated disk drive, and the input and output of the parity generation circuitry. The bus drivers control the placement of data unto the array busses and the direction of the data flow on the array busses.

Abstract: An array controller including a novel data path structure for effecting data transfers between a host computer system bus and four array busses associated with a RAID level 3 disk array without the utilization of a buffer between the host system and the array. The data path structure includes a host register associated with each array bus, each host register being connected to the host bus for receiving data therefrom; a first array register associated with each array bus, each first array register being connected to a corresponding host register for receiving data therefrom and connected to its associated array bus for providing data thereto; and a second array register associated with each array bus, each second array register being connected to it associated array bus for receiving data therefrom and connected to the host bus for providing data thereto.