Patents by Inventor Mahmut Sinangil

Mahmut Sinangil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055048
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 11848047
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Publication number: 20230377614
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
  • Publication number: 20230376273
    Abstract: A compute-in-memory device may include a Booth encoder configured to receive at least one input of first bits, a Booth decoder configured to receive at least one weight of second bits and to output a plurality of partial products of the at least one input and the at least one weight, an adder configured to add a first partial product of the plurality of the partial products and a second partial product of the plurality of partial products before the Booth decoder generates a third partial product of the plurality of the partial products and to generate a plurality of sums of partial products, and a carry-lookahead adder configured to add the plurality of sums of partial products and to generate a final sum.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Rawan Naous, Kerem Akarvardar, Hidehiro Fujiwara, Haruki Mori, Mahmut Sinangil, Yu-Der Chih
  • Publication number: 20230315389
    Abstract: A device includes a first memory cell, a second memory cell, a first logic element, a second logic element, and a third logic element. The first memory cell is configured to store a first bit at a first node, and the second memory cell is configured to store a second bit at a second node. The first logic element includes a first node input terminal coupled to the first node, the second logic element includes a second node input terminal coupled to the second node, and the third logic element includes a first input terminal coupled to a first output terminal of the first logic element and a second input terminal coupled to a second output terminal of the second logic element.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 5, 2023
    Inventors: Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Chia-Fu Lee, Nail Etkin Can AKKAYA, Mahmut Sinangil
  • Patent number: 11763882
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Publication number: 20230290840
    Abstract: The present disclosure describes a structure with front and back side power supply interconnects. The structure includes a transistor structure disposed in a substrate, where the transistor structure includes a source/drain (S/D) region. The structure also includes a front side power supply line above a top surface of the substrate, wherein the front side power supply line is electrically connected to a power supply metal line. The structure further includes a back side power supply line below a bottom surface of the substrate. A front side metal via electrically connects the front side power supply line to a front surface of the S/D region. A back side metal via electrically connects the back side power supply line to a back surface of the S/D region.
    Type: Application
    Filed: April 29, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nail Etkin Can AKKAYA, Mahmut SINANGIL, Yih WANG, Jonathan Tsung-Yung CHANG
  • Publication number: 20230274769
    Abstract: A device includes a memory array formed on a front side of a substrate. The memory array is accessible through a plurality of bit lines. The memory device includes a switch transistor formed on the front side of the substrate. The switch transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on a back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines, in response to the switch transistor being turned off.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 31, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nail Etkin Can Akkaya, Mahmut Sinangil, Yih Wang, Jonathan Tsung-Yung Chang
  • Patent number: 11735235
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
  • Publication number: 20230154507
    Abstract: A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.
    Type: Application
    Filed: January 12, 2023
    Publication date: May 18, 2023
    Inventors: Shang-Chi WU, Yangsyu LIN, Chiting CHENG, Jonathan Tsung-Yung CHANG, Mahmut SINANGIL
  • Publication number: 20230133360
    Abstract: Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.
    Type: Application
    Filed: May 26, 2022
    Publication date: May 4, 2023
    Inventors: Rawan Naous, Kerem Akarvardar, Mahmut Sinangil, Yu-Der Chih, Saman Adham, Nail Etkin Can Akkaya, Hidehiro Fujiwara, Yih Wang, Jonathan Tsung-Yung Chang
  • Publication number: 20230050279
    Abstract: An integrated circuit includes a first encoder, a compute in-memory (CIM) array and a de-encoder. The first encoder is configured to quantize a first received signal into a first signal. The first received signal has a first floating point number format. The first signal has an integer number format. The compute in-memory (CIM) array is coupled to the first encoder. The CIM array is configured to generate a CIM signal in response to at least the first signal. The CIM signal has the integer number format. The de-encoder is coupled to the CIM array, and is configured to generate a first output signal in response to the CIM signal. The first output signal has a second floating point number format.
    Type: Application
    Filed: January 31, 2022
    Publication date: February 16, 2023
    Inventors: Rawan NAOUS, Kerem AKARVARDAR, Hidehiro FUJIWARA, Haruki MORI, Yu-Der CHIH, Mahmut SINANGIL, Yih WANG, Jonathan Tsung-Yung CHANG
  • Patent number: 11562779
    Abstract: A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chi Wu, Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang, Mahmut Sinangil
  • Publication number: 20220359001
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Publication number: 20220302088
    Abstract: A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.
    Type: Application
    Filed: November 29, 2021
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Mahmut Sinangil, Yih Wang
  • Publication number: 20220262424
    Abstract: A computing device in some examples includes an array of memory cells, such as 8-transisor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventor: Mahmut Sinangil
  • Patent number: 11404114
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 11322195
    Abstract: A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Mahmut Sinangil
  • Publication number: 20220130435
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
  • Patent number: 11238906
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang