Patents by Inventor Mahmut Sinangil

Mahmut Sinangil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971217
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Publication number: 20210090621
    Abstract: A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 25, 2021
    Inventors: Shang-Chi WU, Yangsyu LIN, Chiting CHENG, Jonathan Tsung-Yung CHANG, Mahmut SINANGIL
  • Publication number: 20210050053
    Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventors: Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin
  • Publication number: 20210043252
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Publication number: 20200402572
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Patent number: 10867646
    Abstract: A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chi Wu, Chiting Cheng, Jonathan Tsung-Yung Chang, Yangsyu Lin, Mahmut Sinangil
  • Patent number: 10854282
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Publication number: 20200372951
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Application
    Filed: August 12, 2020
    Publication date: November 26, 2020
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Patent number: 10847217
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Patent number: 10847214
    Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin
  • Patent number: 10803928
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10770131
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Publication number: 20200075092
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Publication number: 20190385672
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Application
    Filed: May 17, 2019
    Publication date: December 19, 2019
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 10510403
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Publication number: 20190348110
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 14, 2019
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Publication number: 20190304520
    Abstract: A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Shang-Chi WU, Chiting CHENG, Jonathan Tsung-Yung CHANG, Yangsyu LIN, Mahmut SINANGIL
  • Patent number: 10410715
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: September 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Publication number: 20190237134
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Patent number: 10276231
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil