Patents by Inventor Mahmut Sinangil
Mahmut Sinangil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190304520Abstract: A circuit includes a voltage node, a plurality of memory cells, a bit line coupled with the plurality of memory cells, and a switching circuit coupled between the voltage node and the bit line. The switching circuit is configured to couple the voltage node with the bit line responsive to a voltage level on the bit line.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Shang-Chi WU, Chiting CHENG, Jonathan Tsung-Yung CHANG, Yangsyu LIN, Mahmut SINANGIL
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Patent number: 10410715Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.Type: GrantFiled: February 14, 2018Date of Patent: September 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
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Publication number: 20190237134Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.Type: ApplicationFiled: April 5, 2019Publication date: August 1, 2019Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
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Patent number: 10276231Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.Type: GrantFiled: February 5, 2018Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
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Publication number: 20190108874Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.Type: ApplicationFiled: December 6, 2018Publication date: April 11, 2019Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
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Publication number: 20190096476Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.Type: ApplicationFiled: September 21, 2018Publication date: March 28, 2019Inventors: Yen-Huei Chen, Mahmut Sinangil, Hung-Jen Liao, Tsung-Yung Chang
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Patent number: 10153038Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.Type: GrantFiled: March 5, 2018Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
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Publication number: 20180197601Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
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Publication number: 20180174649Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
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Publication number: 20180158510Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.Type: ApplicationFiled: February 5, 2018Publication date: June 7, 2018Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
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Patent number: 9922701Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.Type: GrantFiled: August 8, 2016Date of Patent: March 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
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Patent number: 9922700Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.Type: GrantFiled: May 24, 2016Date of Patent: March 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
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Publication number: 20180040366Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.Type: ApplicationFiled: August 8, 2016Publication date: February 8, 2018Inventors: Mahmut Sinangil, Chiting Cheng, HUNG-JEN LIAO, Tsung-Yung Chang
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Patent number: 9886996Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled to the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled to the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.Type: GrantFiled: July 28, 2016Date of Patent: February 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
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Publication number: 20170345485Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.Type: ApplicationFiled: May 24, 2016Publication date: November 30, 2017Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
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Publication number: 20170264276Abstract: A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mahmut Sinangil, Hsin-Hsin KO, Chiting CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG
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Patent number: 9762216Abstract: A level shifter circuit is provided that uses a boosting circuit. The boosting circuit is configured to improve the operation of the level shifter circuit when the high voltages of voltage domains across the level shifter circuit are widely separated. A circuit apparatus includes a core level shifter circuit that changes a first voltage of an input signal to a second voltage of an output signal. The circuit apparatus further includes a first boosting circuit that is coupled to the core level shifter circuit and generates a first transient voltage applied to the core level shifter circuit when the input signal transitions from a low value to a high value. The circuit apparatus also includes a second boosting circuit that is coupled to the core level shifter circuit and generates a second transient voltage applied to the core level shifter circuit when the input signal transitions from a high value to a low value.Type: GrantFiled: March 9, 2016Date of Patent: September 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mahmut Sinangil, Hsin-Hsin Ko, Chiting Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang
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Publication number: 20170110181Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.Type: ApplicationFiled: July 28, 2016Publication date: April 20, 2017Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil