Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.

Abstract: Apparatuses, systems, and methods are disclosed for data availability during temporary inaccessibility of a memory region for memory. An apparatus may include a plurality of memory elements and a controller. A controller may be configured to identify a portion of memory of a plurality of memory elements such that data stored in a portion of memory is temporarily inaccessible and other data stored in other portions of memory in the plurality of memory elements is accessible. A controller may be configured to reconstruct data stored in a portion of memory from other data stored in other portions of memory. A controller may be configured to provide reconstructed data while a portion of an array is temporarily inaccessible.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for redundant array of independent disks (RAID) stripe physical placement. An apparatus includes a plurality of memory die comprising physical pages for storing data. An apparatus includes a control circuit that assigns addresses to a plurality of data stripes, wherein the control circuit assigns the addresses to the plurality of data stripes by: assigning stripe pages of a data stripe of the plurality of data stripes to different memory die of a plurality of memory die; and assigning adjacent stripe pages of the data stripe to different page numbers.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for updating data of write-in-place storage devices. One system includes a write-in-place memory device including a redundant storage structure and a controller for the memory device. A memory device is configured to store data across a set of stripes of a redundant storage structure. A controller is configured to receive updated data for a dataset stored across a first stripe, generate a new parity for the dataset based on the updated data, overwrite the dataset across the first stripe with the updated data, and/or write the new parity to the set of stripes.

Abstract: Apparatuses, systems, and methods are disclosed for data availability during temporary inaccessibility of a memory region for memory. An apparatus may include a plurality of memory elements and a controller. A controller may be configured to identify a portion of memory of a plurality of memory elements such that data stored in a portion of memory is temporarily inaccessible and other data stored in other portions of memory in the plurality of memory elements is accessible. A controller may be configured to reconstruct data stored in a portion of memory from other data stored in other portions of memory. A controller may be configured to provide reconstructed data while a portion of an array is temporarily inaccessible.

Abstract: A storage system is provided comprising a memory and a controller. The controller is configured to receive a write command, data, and a logical address; determine a physical address associated with the logical address; generate protection information for the data using the data and at least one of the logical address and physical address; and store the data and the protection information in the memory without storing the at least one of the logical address and physical address in the memory.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for updating data of write-in-place storage devices. One system includes a write-in-place memory device including a redundant storage structure and a controller for the memory device. A memory device is configured to store data across a set of stripes of a redundant storage structure. A controller is configured to receive updated data for a dataset stored across a first stripe, generate a new parity for the dataset based on the updated data, overwrite the dataset across the first stripe with the updated data, and/or write the new parity to the set of stripes.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for redundant array of independent disks (RAID) stripe physical placement. An apparatus includes a plurality of memory die comprising physical pages for storing data. An apparatus includes a control circuit that assigns addresses to a plurality of data stripes, wherein the control circuit assigns the addresses to the plurality of data stripes by: assigning stripe pages of a data stripe of the plurality of data stripes to different memory die of a plurality of memory die; and assigning adjacent stripe pages of the data stripe to different page numbers.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.

Abstract: A storage system is provided comprising a memory and a controller. The controller is configured to receive a write command, data, and a logical address; determine a physical address associated with the logical address; generate protection information for the data using the data and at least one of the logical address and physical address; and store the data and the protection information in the memory without storing the at least one of the logical address and physical address in the memory.

Abstract: An apparatus includes a heat pipe with a fluid path. A first part of the fluid path is thermally coupled to a first region of a higher temperature and a second part of the fluid path thermally is coupled to a second region of a lower temperature. A difference between the higher temperature and the lower temperature induces a flow of a magnetic fluid in the fluid path. A switchable magnetic device is magnetically coupled to the fluid path. Activation of the switchable magnetic device reduces the flow of the magnetic fluid in the fluid path, which reduces heat transfer from the first region to the second region.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string.

Abstract: A group of non-volatile, solid state memory cells are transferred from an active list that includes memory cells accessible to a host to a temporary list that includes memory cells temporarily inaccessible to the host. The memory cells included in the temporary list are maintained at a temperature that is substantially the same as or lower than that of memory cells included in the active list. The memory cells are transferred from the temporary list to the active list in response to satisfaction of a trigger condition.

Abstract: An apparatus includes a heat pipe with a fluid path. A first part of the fluid path is thermally coupled to a first region of a higher temperature and a second part of the fluid path thermally is coupled to a second region of a lower temperature. A difference between the higher temperature and the lower temperature induces a flow of a magnetic fluid in the fluid path. A switchable magnetic device is magnetically coupled to the fluid path. Activation of the switchable magnetic device reduces the flow of the magnetic fluid in the fluid path, which reduces heat transfer from the first region to the second region.

Abstract: Some embodiments involve a method of detecting an error of a memory device. It is determined whether the detected error is a catastrophic error. If it is determined that the error is a catastrophic error, an error recovery process is bypassed. Some aspects involve a method of detecting an error of a memory device. It is determined whether a counter value is above a predetermined value. If it is determined that the counter value is above the predetermined value an error recovery process is bypassed and a redundant parity recovery process is performed.

Abstract: An error of a solid-state non-volatile memory is detected. It is determined whether a type of the error is a first type of error. A voltage recovery process is bypassed based on whether the error is the first type of error. If it is determined that the error is a catastrophic error, the voltage error recovery process is bypassed. If it is determined that an offset of a threshold voltage is not greater than a predetermined value, the voltage error recovery process is bypassed.

Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.

Abstract: Various embodiments of a method and system for preserving data of a data storage device are disclosed. The method can include determining a number of times data is written to a target track of a storage medium; rewriting data from a track adjacent the target track if the number of times data is written to the target track exceeds a first predetermined threshold; determining a number of times data is rewritten to the adjacent track; copying data from the target track to a first storage location of a media cache if the number of times data is rewritten to the adjacent track exceeds a second predetermined threshold; writing subsequent data designated for the target track to the first storage location of the media cache; and relocating data from the first storage location of the media cache to the target track.

Abstract: A method and system for preserving data of a storage device are disclosed. In one embodiment, the method includes determining a number of times data is written to a first track in a first region of a storage medium, and rewriting data from a second track that is adjacent to the first track in the first region if the number of times data is written to the first track in the first region exceeds a first predetermined threshold. The method further includes determining a number of times data is rewritten to the second track in the first region, and relocating data from the second track in the first region to a second region of the storage medium if the number of times data is rewritten to the second track in the first region exceeds a second predetermined threshold.