Abstract: Various embodiments of a method and system for preserving data of a data storage device are disclosed. The method can include determining a number of times data is written to a target track of a storage medium; rewriting data from a track adjacent the target track if the number of times data is written to the target track exceeds a first predetermined threshold; determining a number of times data is rewritten to the adjacent track; copying data from the target track to a first storage location of a media cache if the number of times data is rewritten to the adjacent track exceeds a second predetermined threshold; writing subsequent data designated for the target track to the first storage location of the media cache; and relocating data from the first storage location of the media cache to the target track.

Abstract: A method and system for preserving data of a storage device are disclosed. In one embodiment, the method includes determining a number of times data is written to a first track in a first region of a storage medium, and rewriting data from a second track that is adjacent to the first track in the first region if the number of times data is written to the first track in the first region exceeds a first predetermined threshold. The method further includes determining a number of times data is rewritten to the second track in the first region, and relocating data from the second track in the first region to a second region of the storage medium if the number of times data is rewritten to the second track in the first region exceeds a second predetermined threshold.

Abstract: Various embodiments of a method and system for preserving data of a data storage device are disclosed. The method can include determining a number of times data is written to a target track of a storage medium; rewriting data from a track adjacent the target track if the number of times data is written to the target track exceeds a first predetermined threshold; determining a number of times data is rewritten to the adjacent track; copying data from the target track to a first storage location of a media cache if the number of times data is rewritten to the adjacent track exceeds a second predetermined threshold; writing subsequent data designated for the target track to the first storage location of the media cache; and relocating data from the first storage location of the media cache to the target track.

Abstract: An adaptive search scheme leads to threshold voltages that have lower bit error rates over initial values. An initial reference voltage is used and data is measured for set steps in voltage about the initial value sufficient to fit a polynomial curve. A minimum is used to determine the lowest bit error rate and corresponding optimum threshold voltage. This voltage is adopted as the new threshold voltage for reading the given data.

Abstract: Apparatus and method for adaptively mitigating adjacent track interference (ATI) effects on a data recording medium. In some embodiments, a write count value is accumulated for a first track responsive to successive writes to a second track on the data recording medium. For each of the successive writes, the accumulated write count value for the first track is incremented by a different variable amount based on temperature. The first track is refreshed responsive to the accumulated write count reaching a selected threshold value.

Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.

Abstract: An error of a solid-state non-volatile memory is detected. It is determined whether a type of the error is a first type of error. A voltage recovery process is bypassed based on whether the error is the first type of error. If it is determined that the error is a catastrophic error, the voltage error recovery process is bypassed. If it is determined that an offset of a threshold voltage is not greater than a predetermined value, the voltage error recovery process is bypassed.

Abstract: Some embodiments involve a method of detecting an error of a memory device. It is determined whether the detected error is a catastrophic error. If it is determined that the error is a catastrophic error, an error recovery process is bypassed. Some aspects involve a method of detecting an error of a memory device. It is determined whether a counter value is above a predetermined value. If it is determined that the counter value is above the predetermined value an error recovery process is bypassed and a redundant parity recovery process is performed.

Abstract: A method and system for preserving data of a storage device are disclosed. In one embodiment, the method includes determining a number of times data is written to a first track in a first region of a storage medium, and rewriting data from a second track that is adjacent to the first track in the first region if the number of times data is written to the first track in the first region exceeds a first predetermined threshold. The method further includes determining a number of times data is rewritten to the second track in the first region, and relocating data from the second track in the first region to a second region of the storage medium if the number of times data is rewritten to the second track in the first region exceeds a second predetermined threshold.

Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.

Abstract: A group of non-volatile, solid state memory cells are transferred from an active list that includes memory cells accessible to a host to a temporary list that includes memory cells temporarily inaccessible to the host. The memory cells included in the temporary list are maintained at a temperature that is substantially the same as or lower than that of memory cells included in the active list. The memory cells are transferred from the temporary list to the active list in response to satisfaction of a trigger condition.

Abstract: A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.

Abstract: An adaptive search scheme leads to threshold voltages that have lower bit error rates over initial values. An initial reference voltage is used and data is measured for set steps in voltage about the initial value sufficient to fit a polynomial curve. A minimum is used to determine the lowest bit error rate and corresponding optimum threshold voltage. This voltage is adopted as the new threshold voltage for reading the given data.

Abstract: A method is provided that decides whether a region of data storage units in a data storage system should be scanned for defective data. A current region of data storage units affected by a write operation is determined and which select transducing head of the data storage system that corresponds with the current region is also determined. A scalar value that corresponds with the select transducing head is retrieved. The scalar value related to a condition of the select transducing head based on previously conducted performance tests. An incremented write count of the affected region is scaled by the scalar value to obtain a new increment write count. A defective data scan is performed on the affected region if the new increment write count exceeds a default write count threshold.

Abstract: A transducing head has a magnetoresistive sensor and a first and a second dual path conductor/magnet structure for providing current to the magnetoresistive sensor and for stabilizing the magnetoresistive sensor. The first and the second dual path conductor/magnet structures are arranged in an abutted-junction configuration on opposite sides of the magnetoresistive sensor. Each of the first and the second dual path conductor/magnet structures has at least one bias layer and at least one conductor layer. Each bias layer is formed upon a bias seed layer positioned over one of the conductor layers. Each bias seed layer is selected to result in the bias layer formed upon it having a coercivity between about 1 kOe and about 5 kOe and an in-plane remnant squareness greater than about 0.8. Most preferably, each of the first and the second dual path conductor/magnet structures is formed of at least two conductor layers interspersed with at least one bias layer.

Abstract: A transducing head has a magnetoresistive sensor and first and second permanent magnet bias elements for providing longitudinal bias to the magnetoresistive sensor. The first and second permanent magnet bias elements are arranged on opposite sides of the magnetoresistive sensor and recessed a distance away from the magnetoresistive sensor. The transducing head of the present invention achieves increased read sensitivity by recessing the first and second permanent magnet bias elements away from the magnetoresistive sensor.

Abstract: A transducing head has a magnetoresistive sensor and a first and a second dual path conductor/magnet structure for providing current to the magnetoresistive sensor and for stabilizing the magnetoresistive sensor. The first and the second dual path conductor/magnet structures are arranged in an abutted-junction configuration on opposite sides of the magnetoresistive sensor. Each of the first and the second dual path conductor/magnet structures has at least one bias layer and at least one conductor layer. Each bias layer is formed upon a bias seed layer positioned over one of the conductor layers. Each bias seed layer is selected to result in the bias layer formed upon it having a coercivity between about 1 kOe and about 5 kOe and an in-plane remnant squareness greater than about 0.8. Most preferably, each of the first and the second dual path conductor/magnet structures is formed of at least two conductor layers interspersed with at least one bias layer.